BTC

BTC copies one bit of its first operand into CF and then inverts that bit. The bit is chosen as BT chooses it, and ZF stays as it was. Of the three bit-modifying siblings it is the least used: BTS sets and BTR clears, and both have obvious uses as locks and claims. Flipping is for toggles: a phase bit that alternates between two buffers, or the sign bit of an integer.

The new value from the old#

CF holds the bit as it was, so after BTC the bit as it is now is the inverse of CF. GCC 14 and Clang 23 at -O2 compile the atomic toggle __atomic_xor_fetch(p, m, __ATOMIC_SEQ_CST) & m, with m being 1UL << (n & 63), to and esi, 63, lock btc qword ptr [rdi], rsi and setnc al (Clang prints setae al): the condition is inverted, not the instruction. With __atomic_fetch_xor, which returns the old value, they use SETC as for BTS. The AND stays because a memory operand does not reduce the bit number modulo 64.

On registers#

x ^ (1UL << n) becomes btc rax, rsi with both compilers. For the sign bit of a 64-bit value, x ^ (1UL << 63), GCC emits btc rax, 63, and Clang a 10-byte MOVABS of the mask and an XOR. For a 32-bit x ^ 0x80000000, both use lea eax, [rdi - 2147483648]: adding 2^31 flips bit 31 too, and LEA writes the result to another register without touching the flags.

Things to know#

• Speed. AMD’s Zen 5 instruction table lists the register forms of BTC as 2 macro-ops and every memory form as microcoded; for plain memory, compilers flip a bit with an XOR to memory instead.
• LOCK is accepted only with a memory destination, and raises #UD on a register.
• Undefined flags. OF, SF, AF and PF are undefined; Zen 5 left them as they were in all 168 recorded cases.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = bit & (OSIZE - 1)            # the offset, modulo the operand size
v = dest.read()                  # with LOCK: one atomic read-modify-write
cf = v >> n & 1
of = sf = af = pf = UNDEFINED    # ZF keeps its value
dest.write(v ^ 1 << n)           # a 32-bit register: bits 63:32 cleared

n = signed(bit)                  # not masked: bit n can lie far below
                                 # or above the operand
a = dest.address + n // OSIZE * (OSIZE // 8)   # the OSIZE bits that
v = load(a, OSIZE)                             # hold it; with LOCK,
cf = v >> n % OSIZE & 1                        # read and written as one
of = sf = af = pf = UNDEFINED    # ZF keeps its value
store(a, OSIZE, v ^ 1 << n % OSIZE)

Operands

Flags

Attributes

What else XED records about the forms. How to read.

Memory forms without LOCK

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions