BTR

BTR copies one bit of its first operand into CF and then clears that bit. It is BTS with the opposite write: the bit is chosen as BT chooses it, ZF stays as it was, and with LOCK on a memory operand the read, the clear and the write back are one atomic operation. CF then says whether this BTR was the one that cleared the bit, which makes it a test-and-clear: a thread can claim a slot marked free by a set bit, or consume a pending-event bit, and know that no other thread got the same one.

From C#

GCC 14 and Clang 23 at -O2 compile __atomic_fetch_and(p, ~(1UL << 40), __ATOMIC_SEQ_CST) & (1UL << 40) to lock btr qword ptr [rdi], 40 and a SETC (Clang prints it setb), and the same with a bit number n in a register to and esi, 63 and lock btr qword ptr [rdi], rsi: the AND stays because a memory operand does not take the offset modulo 64. Without the test of the old bit, both emit lock and with a mask instead.

On a register, x & ~(1UL << n) becomes btr rax, rsi. For a constant bit above 31, such as 40 or the sign bit 63, GCC writes btr rax, 40, while Clang loads the inverted mask with a 10-byte MOVABS and ANDs it, since an AND immediate holds at most 32 bits, sign-extended.

Clearing a bit in memory#

Neither compiler uses BTR on plain memory. For a[n / 64] &= ~(1UL << (n % 64)), GCC builds the mask with a shift and a NOT, and Clang with mov rax, -2 and rol rax, cl, rotating the one zero into place, before an AND to memory. The instruction table of AMD’s Zen 5 guide lists every memory form of BTR as microcoded and the register forms as 2 macro-ops.

Things to know#

• Not the lowest bit. To clear the lowest set bit, whichever it is, BLSR does it without a bit number.
• Undefined flags. OF, SF, AF and PF are undefined; Zen 5 left them as they were in all 168 recorded cases.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = bit & (OSIZE - 1)            # the offset, modulo the operand size
v = dest.read()                  # with LOCK: one atomic read-modify-write
cf = v >> n & 1
of = sf = af = pf = UNDEFINED    # ZF keeps its value
dest.write(v & ~(1 << n))        # a 32-bit register: bits 63:32 cleared

n = signed(bit)                  # not masked: bit n can lie far below
                                 # or above the operand
a = dest.address + n // OSIZE * (OSIZE // 8)   # the OSIZE bits that
v = load(a, OSIZE)                             # hold it; with LOCK,
cf = v >> n % OSIZE & 1                        # read and written as one
of = sf = af = pf = UNDEFINED    # ZF keeps its value
store(a, OSIZE, v & ~(1 << n % OSIZE))

Operands

Flags

Attributes

What else XED records about the forms. How to read.

Memory forms without LOCK

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTC
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions