BTS

BTS copies one bit of its first operand into CF and then sets that bit to 1. It selects the bit as BT does, so a register offset on a memory operand can reach far outside the addressed word, and it leaves ZF alone. BTR clears the bit instead and BTC flips it.

Test-and-set#

With LOCK and a memory operand, BTS reads, sets and writes back as one atomic operation, and CF tells whether the bit was already set: a one-bit test-and-set, for a bitmap of free slots or a flag that only one thread may claim. GCC 14 and Clang 23 at -O2 compile __atomic_fetch_or(p, 1UL << n, __ATOMIC_SEQ_CST) & (1UL << n) to lock bts qword ptr [rdi], rsi and a SETC (Clang prints it setb), and a constant bit 5 to lock bts qword ptr [rdi], 5. When the old value is not used at all, they emit lock or instead.

The mask the compilers keep#

Written as 1UL << (n & 63), that call still gets an and esi, 63 before the LOCK BTS from both compilers, while x | (1UL << (n & 63)) on a register becomes a bare bts rax, rsi. A register operand takes the offset modulo 64 by itself; a memory operand does not, and an unmasked RSI would set a bit in another word of memory. In Zen 5’s cases, an offset of -512 set bit 0 of the byte 64 bytes below the address, and LOCK BTS with 511 set bit 7 of the byte 63 bytes above it.

On registers, GCC also sets a constant bit such as 40 with bts rax, 40, where Clang loads the mask with a 10-byte MOVABS and ORs it in.

Things to know#

• Speed. The instruction table of AMD’s Zen 5 guide lists the register forms as 2 macro-ops and every memory form, with an immediate or a register offset, as microcoded. Neither compiler uses BTS on plain memory at -O2: a[n / 64] |= 1UL << (n % 64) becomes a shift and an OR to memory.
• Undefined flags. OF, SF, AF and PF are undefined; Zen 5 left them as they were in all 168 recorded cases.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = bit & (OSIZE - 1)            # the offset, modulo the operand size
v = dest.read()                  # with LOCK: one atomic read-modify-write
cf = v >> n & 1
of = sf = af = pf = UNDEFINED    # ZF keeps its value
dest.write(v | 1 << n)           # a 32-bit register: bits 63:32 cleared

n = signed(bit)                  # not masked: bit n can lie far below
                                 # or above the operand
a = dest.address + n // OSIZE * (OSIZE // 8)   # the OSIZE bits that
v = load(a, OSIZE)                             # hold it; with LOCK,
cf = v >> n % OSIZE & 1                        # read and written as one
of = sf = af = pf = UNDEFINED    # ZF keeps its value
store(a, OSIZE, v | 1 << n % OSIZE)

Operands

Flags

Attributes

What else XED records about the forms. How to read.

Memory forms without LOCK

accepts a LOCK prefix

LOCK forms

locked: atomic read-modify-write; accepts XACQUIRE; accepts XRELEASE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAA
• AAD
• AAM
• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTC
• BTR
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMP
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS

All 109 General-purpose instructions