BZHI

BZHI keeps the low n bits of its source and clears the others, n being the index in the third operand: bzhi eax, edi, esi computes EDI with every bit from position ESI up cleared. It is the C expression x & ((1ULL << n) - 1) in one instruction, and with -march=x86-64-v3 GCC 14 and Clang 23 at -O2 compile it, for 32 and 64 bits, to a single BZHI. With SHRX it extracts a field whose start and length are variables, (x >> s) & ((1ULL << n) - 1), which both compilers prefer to BEXTR.

The index#

Only bits 7:0 of the index register count, read as a number from 0 to 255:

• n = 0 gives 0;
• n from the operand size to 255 keeps every bit and sets CF, so BZHI is defined where C’s 1u << 32 is not;
• the bits above 7:0 are ignored: on Zen 5, BZHI of all ones with the index 0x105 gave 0x1F, five bits, and the index 0x100 gave 0 from C4658624H.

Both manuals say in their text that a large index saturates at the operand size minus 1, which, read with AMD’s rule that the bits from the index up are cleared, would clear the top bit. Intel’s Operation section clears nothing in that case, and neither did Zen 5: an index of 32 or 255 left a 32-bit source of all ones as it was.

CF and ZF#

CF says whether the index was at least the operand size; SF and ZF follow the result, OF is cleared, and AF and PF are undefined.

Speed#

Intel’s optimization manual places BZHI among the instructions of the two bit-manipulation units of Golden Cove (Table 2-4); the instruction table of AMD’s Zen 5 guide lists it as one macro-op with a latency of one cycle.

BZHI belongs to BMI2, part of x86-64-v3; APX adds an EVEX form and one that leaves the flags unchanged (NF).

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

n = index & 0xFF                 # bits 7:0 of the index register
r = src & (1 << n) - 1           # bits n and up cleared: none when n is
                                 # OSIZE or more
if not nf:                       # NF=1 (APX) leaves the flags as they were
    cf = n >= OSIZE
    sf = msb(r)
    zf = r == 0
    of = 0
    af = pf = UNDEFINED
dest.write(r)                    # a 32-bit register: bits 63:32 cleared

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

none in XED

EVEX forms

APX-EVEX-BMI

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to BZHI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More BMI2 instructions

• MULX
• PDEP
• PEXT
• RORX
• SARX
• SHLX
• SHRX

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions