CBW instruction (General-purpose)

CBW sign-extends AL into AX: every bit of AH becomes a copy of bit 7 of AL. It is opcode 98 with a 66 prefix, two bytes, and AT&T syntax calls it cbtw. Like any 16-bit write it leaves bits 63:16 of RAX as they were: Zen 5 turned AL = 80H into AX = FF80H and AL = 7FH into 007FH, and in each of its 8 recorded cases kept the upper 48 bits. It changes no flag. CQO has the table of the whole family.

Before a byte division

CBW makes the dividend of a byte division: an 8-bit IDIV divides AX by its operand, so a signed byte in AL has to be widened first, as CWD widens a word for a 16-bit division. C promotes signed char and short to int before dividing, and GCC 14 and Clang 23 at -O2 divide them in 32 bits with CDQ, or, Clang for signed char, in 16 bits with CWD: neither emits a byte division.

Where it still appears

GCC uses CBW where a function returns a short made from a signed char that a call left in AL: short f(void) { return gc(); } compiles to call gc and cbw. Clang emits movsx eax, al for the same function, which writes the whole of EAX and so clears bits 63:32 as well; the caller looks only at AX either way. For an int result both compilers use MOVSX, as CBW cannot reach beyond AX.

Within the family

The same byte 98 without the 66 prefix is CWDE, and with REX.W CDQE; a REX.W prefix wins over 66, so 66 48 98 is still CDQE. MOVSX does what CBW does with any registers, in three bytes or more. The instruction table of AMD’s Zen 5 guide lists CBW as one macro-op with a latency of 1.

Forms

Every encoding of CBW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CBW` CBW	`66 98`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CBW`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.25p0156
Alder Lake, Sapphire Rapids	1 / 0.5p15
Lunar Lake	1 / 0.5V2 V3
Bonnell	4 / 2p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

ax = sext(al, 8)                 # bits 63:16 of RAX stay

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CBW`
`AX`	implicit	write
`AL`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Before a byte division#

Where it still appears#

Within the family#