CCMPscc

CCMPscc lets a compiler evaluate a chain of comparisons such as a == 1 && b > c without a branch per term. The source condition (scc, one of the usual condition codes) is tested against the current flags:

• If it holds, the instruction is an ordinary CMP and sets the flags from the comparison.
• If it does not, the comparison is skipped. OF, SF, ZF and CF are set from the four-bit default flags value (dfv) in the instruction, PF is set equal to CF, and AF is cleared.

Two extra condition codes replace the parity conditions: T (always true) makes CCMPT an ordinary compare, and F (always false) sets the flags to dfv unconditionally. A memory operand may fault even when the condition is false. CTESTscc is the same idea for TEST.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src1.read()                  # memory is read, and can fault, even
b = sext(src2)                   # when the condition is false
if cond(CC):
    flags = sub_flags(a, b)      # as CMP src1, src2
else:
    of = dfv >> 3 & 1            # the flags of {dfv}
    sf = dfv >> 2 & 1
    zf = dfv >> 1 & 1
    cf = dfv & 1
    pf = dfv & 1                 # PF as CF
    af = 0

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

APX-EVEX-CCMP

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions