x86-64.net

Instruction

CCMPscc

APX conditional compare: if the flags meet a condition, compares two operands, otherwise sets OF, SF, ZF and CF to a value in the instruction.

Extensions
Mnemonics
CCMPO, CCMPNO, CCMPB, CCMPC, CCMPNAE, CCMPNB, CCMPNC, CCMPAE, CCMPZ, CCMPE, CCMPNZ, CCMPNE, CCMPBE, CCMPNA, CCMPNBE, CCMPA, CCMPS, CCMPNS, CCMPT, CCMPF, CCMPL, CCMPNGE, CCMPNL, CCMPGE, CCMPLE, CCMPNG, CCMPNLE, CCMPG
Forms
12 (12 EVEX)
Data
Intel XED v2026.08.23

CCMPscc lets a compiler evaluate a chain of comparisons such as a == 1 && b > c without a branch per term. The source condition (scc, one of the usual condition codes) is tested against the current flags:

  • If it holds, the instruction is an ordinary CMP and sets the flags from the comparison.
  • If it does not, the comparison is skipped. OF, SF, ZF and CF are set from the four-bit default flags value (dfv) in the instruction, PF is set equal to CF, and AF is cleared.

Two extra condition codes replace the parity conditions: T (always true) makes CCMPT an ordinary compare, and F (always false) sets the flags to dfv unconditionally. A memory operand may fault even when the condition is false. CTESTscc is the same idea for TEST.

Forms

Every encoding of CCMPscc that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CCMPscc {dfv} r8, r8 CCMPscc_GPR8i8_GPR8i8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 38 /r SC=scc
EVEX.LLZ.NP.MAP4.WIG 3A /r SC=scc		APX_F + APX_NCI_NDD_NF
CCMPscc {dfv} m8, r8 CCMPscc_MEMi8_GPR8i8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 38 /r SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r16/32/64, imm8 CCMPscc_GPRv_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /7 ib SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} m16/32/64, imm8 CCMPscc_MEMv_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 83 /7 ib SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r16/32/64, r16/32/64 CCMPscc_GPRv_GPRv_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 39 /r SC=scc
EVEX.LLZ.NP.MAP4.SCALABLE 3B /r SC=scc		APX_F + APX_NCI_NDD_NF
CCMPscc {dfv} m16/32/64, r16/32/64 CCMPscc_MEMv_GPRv_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 39 /r SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r8, m8 CCMPscc_GPR8i8_MEMi8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 3A /r SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r16/32/64, m16/32/64 CCMPscc_GPRv_MEMv_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 3B /r SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r8, imm8 CCMPscc_GPR8i8_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /7 ib SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} m8, imm8 CCMPscc_MEMi8_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 80 /7 ib SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} r16/32/64, imm16/32 CCMPscc_GPRv_IMMz_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /7 iw/id SC=sccAPX_F + APX_NCI_NDD_NF
CCMPscc {dfv} m16/32/64, imm16/32 CCMPscc_MEMv_IMMz_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 81 /7 iw/id SC=sccAPX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.