CDQ instruction (General-purpose)

CDQ fills EDX with copies of the sign bit of EAX, so that EDX:EAX holds the value of EAX as a signed 64-bit number, the dividend of a 32-bit IDIV. It is the one-byte opcode 99; AT&T syntax calls it cltd. Being a 32-bit write in 64-bit mode, it clears bits 63:32 of RDX: in Zen 5’s 8 recorded cases RDX became either 0 or 00000000FFFFFFFFH, whatever it held. It changes no flag, and it leaves RAX alone.

Before every signed int division

It is among the most common instructions in compiled division code. GCC 14 and Clang 23 at -O2 compile a / b on two ints to mov eax, edi, cdq and idiv esi, and a % b to the same three with the remainder taken from EDX. Divisions of short take the same path, as C converts them to int first; for signed char, Clang divides in 16 bits with CWD instead. The 64-bit counterpart is CQO, whose page also covers the unsigned case, where xor edx, edx must replace CDQ before DIV.

Sign masks without it

CDQ is a sign mask, 0 or -1, in one byte, but only from EAX into EDX. Compilers no longer build other idioms on it: for x >> 31 both use mov eax, edi and sar eax, 31, which works in any register, and for the absolute value of an int they emit neg eax and cmovs eax, edi rather than the old CDQ, XOR and SUB sequence. A division by a power of two, such as a / 2, is a shift with a correction for negative numbers (shr eax, 31, an ADD and sar eax), with no CDQ either.

Cost

Intel’s optimization manual notes that CDQ costs as many micro-ops as the MOV and shift it stands for, being only shorter, and suggests xor edx, edx when EAX is known not to be negative (Section 3.5.1.1).

In the optimization guide

What the optimization guide says about CDQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

Integer execution: xor edx, edx before DIV, or CDQ or CQO before IDIV, with the same operand size and a divisor in a register other than rDX, saves a macro-op: the pair is dispatched as one fewer.

Forms

Every encoding of CDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CDQ` CDQ	`99`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CDQ`
Sandy Bridge	1 / 0.5p05
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids	1 / 0.5p06
Lunar Lake	1 / 0.33p024
Bonnell	4 / 2p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

edx = -1 if msb(eax) else 0      # bits 63:32 of RDX cleared

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CDQ`
`EDX`	implicit	write
`EAX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I386` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Before every signed int division#

Sign masks without it#

Cost#