CDQE instruction (General-purpose)

CDQE sign-extends EAX into RAX: bits 63:32 become copies of bit 31. It is opcode 98 with REX.W, two bytes (48 98), and does for RAX alone what MOVSXD rax, eax does in three (48 63 C0). AT&T syntax calls it cltq. It changes no flag. CQO has the table of the whole family, from CBW to CQO.

Where compilers use it

GCC 14 and Clang 23 at -O2 emit CDQE when the int to widen is already in EAX, which mostly means the value a call returned: long f(void) { return g(); }, with g returning int, compiles to call g and cdqe, and a[g()] does the same before the index can enter the address. An int that arrives in another register, such as an argument in EDI, gets movsxd rax, edi instead, which moves and extends in one instruction.

Not the same as clearing the upper half

Any write to EAX clears bits 63:32 of RAX, and compilers widen an unsigned return value with mov eax, eax for that reason. CDQE fills those bits from bit 31 instead, whatever they held: in Zen 5’s 8 recorded cases, 80000000H under random upper bits became FFFFFFFF80000000H and 7FFFFFFFH became 000000007FFFFFFFH. Mixing the two up changes every negative int into a number above 4 billion.

One opcode, three sizes

Without REX.W the same byte 98 is CWDE, which extends AX into EAX and so clears bits 63:32 as a 32-bit write; with a 66 prefix it is CBW, which extends AL into AX and keeps the rest of RAX. CDQE exists only in 64-bit mode, the only mode with REX.W.

The instruction table of AMD’s Zen 5 guide lists CDQE as one macro-op with a latency of 1 and a throughput of one per cycle, against six per cycle for MOVSXD, MOVSX and a MOV between registers.

Forms

Every encoding of CDQE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CDQE` 64-bit mode only CDQE	`REX.W 98`	LM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CDQE`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.25p0156
Alder Lake, Sapphire Rapids	1 / 0.5p15
Lunar Lake	1 / 0.5V2 V3
Bonnell	4 / 2p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

rax = sext(eax, 32)

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CDQE` 64-bit mode only
`RAX`	implicit	write
`EAX`	implicit	read

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`LONGMODE` General-purpose System SYSCALL/SYSRET	LM `CPUID.80000001H:EDX[29]` LM	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Where compilers use it#

Not the same as clearing the upper half#

One opcode, three sizes#