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Instruction

CFCMOVcc

APX conditionally faulting move: on a false condition, memory is untouched and cannot fault; a register destination gets zero, or a source with NDD.

Extensions
Mnemonics
CFCMOVO, CFCMOVNO, CFCMOVB, CFCMOVC, CFCMOVNAE, CFCMOVNB, CFCMOVNC, CFCMOVAE, CFCMOVZ, CFCMOVE, CFCMOVNZ, CFCMOVNE, CFCMOVBE, CFCMOVNA, CFCMOVNBE, CFCMOVA, CFCMOVS, CFCMOVNS, CFCMOVP, CFCMOVPE, CFCMOVNP, CFCMOVPO, CFCMOVL, CFCMOVNGE, CFCMOVNL, CFCMOVGE, CFCMOVLE, CFCMOVNG, CFCMOVNLE, CFCMOVG
Forms
5 (5 EVEX)
Data
Intel XED v2026.08.23

Legacy CMOVcc raises memory faults even when its condition is false, so a load from an address that is only valid when the condition holds cannot become a CMOVcc. CFCMOVcc (“conditionally faulting”) fixes that. When the condition is false, a memory operand is not accessed and cannot fault.

The EVEX ND and NF bits select four variants, and three of them are CFCMOVcc:

NDNFFormWhen the condition is false
00CFCMOVcc reg, r/mreg becomes zero; a memory source is not read
01CFCMOVcc r/m, rega register destination becomes zero; a memory destination is not written
10CMOVcc ndd, reg, r/mndd gets reg; the memory source is still read and may fault
11CFCMOVcc ndd, reg, r/mndd gets reg; a memory source is not read

The ND=0, NF=1 form is a conditional store: with a memory destination, nothing is written when the condition is false. As with NDD instructions, a register destination narrower than 64 bits is zero-extended.

Forms

Every encoding of CFCMOVcc that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CFCMOVcc r16/32/64, r16/32/64 NF optional CFCMOVcc_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r NF=0/1APX_F + APX_NCI_NDD_NF
CFCMOVcc r16/32/64, m16/32/64 CFCMOVcc_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /rAPX_F + APX_NCI_NDD_NF
CFCMOVcc m16/32/64, r16/32/64 NF CFCMOVcc_MEMv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r NF=1APX_F + APX_NCI_NDD_NF
CFCMOVcc r16/32/64, r16/32/64, r16/32/64 NDD NF CFCMOVcc_GPRv_GPRv_GPRv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 NF=1APX_F + APX_NCI_NDD_NF
CFCMOVcc r16/32/64, r16/32/64, m16/32/64 NDD NF CFCMOVcc_GPRv_GPRv_MEMv_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 NF=1APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.