CFCMOVcc instruction (APX)

Legacy CMOVcc raises memory faults even when its condition is false, so a load from an address that is only valid when the condition holds cannot become a CMOVcc. CFCMOVcc (“conditionally faulting”) fixes that. When the condition is false, a memory operand is not accessed and cannot fault.

The EVEX ND and NF bits select four variants, and three of them are CFCMOVcc:

ND	NF	Form	When the condition is false
0	0	CFCMOVcc reg, r/m	reg becomes zero; a memory source is not read
0	1	CFCMOVcc r/m, reg	a register destination becomes zero; a memory destination is not written
1	0	CMOVcc ndd, reg, r/m	ndd gets reg; the memory source is still read and may fault
1	1	CFCMOVcc ndd, reg, r/m	ndd gets reg; a memory source is not read

The ND=0, NF=1 form is a conditional store: with a memory destination, nothing is written when the condition is false. As with NDD instructions, a register destination narrower than 64 bits is zero-extended.

Forms

Every encoding of CFCMOVcc that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CFCMOVcc r16/32/64, r16/32/64` NF optional CFCMOVcc_GPRv_GPRv_APX_N3	`EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r NF=0/1`	APX_F + APX_NCI_NDD_NF
`CFCMOVcc r16/32/64, m16/32/64` CFCMOVcc_GPRv_MEMv_APX_N3	`EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r`	APX_F + APX_NCI_NDD_NF
`CFCMOVcc m16/32/64, r16/32/64` NF CFCMOVcc_MEMv_GPRv_APX_N3	`EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r NF=1`	APX_F + APX_NCI_NDD_NF
`CFCMOVcc r16/32/64, r16/32/64, r16/32/64` NDD NF CFCMOVcc_GPRv_GPRv_GPRv_APX_N3	`EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 NF=1`	APX_F + APX_NCI_NDD_NF
`CFCMOVcc r16/32/64, r16/32/64, m16/32/64` NDD NF CFCMOVcc_GPRv_GPRv_MEMv_APX_N3	`EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 NF=1`	APX_F + APX_NCI_NDD_NF

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

All forms but the NDD forms

if cond(CC):
    dest.write(src)              # a register destination: bits 63:OSIZE
                                 # cleared, even for 16 bits
elif not dest.is_memory:
    dest.write(0)                # a register is cleared all the same
# when the condition is false, memory is neither read nor written,
# and cannot fault

Not run on a processor: none of these processors has APX.

NDD forms

if cond(CC):
    dest.write(src2)
else:
    dest.write(src1)             # memory is not read, and cannot fault
# the new destination: bits 63:OSIZE cleared, even for 16 bits

Not run on a processor: none of these processors has APX.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CFCMOVcc r16/32/64, r16/32/64` NF optional
`r16/32/64`	explicit	write
`r16/32/64`	explicit	read
`RFLAGS`	implicit	read
`CFCMOVcc r16/32/64, m16/32/64`
`r16/32/64`	explicit	write
`m16/32/64`	explicit	read
`RFLAGS`	implicit	read
`CFCMOVcc m16/32/64, r16/32/64` NF
`m16/32/64`	explicit	conditional write
`r16/32/64`	explicit	read
`RFLAGS`	implicit	read
`CFCMOVcc r16/32/64, r16/32/64, r/m16/32/64` NDD NF
`r16/32/64`	explicit	write
`r16/32/64`	explicit	read
`r/m16/32/64`	explicit	read
`RFLAGS`	implicit	read

Flags

T tested; blank: not affected. How to read.

When	OF	SF	ZF	PF	CF
All forms
CFCMOVB					T
CFCMOVBE			T		T
CFCMOVL	T	T
CFCMOVLE	T	T	T
CFCMOVNB					T
CFCMOVNBE			T		T
CFCMOVNL	T	T
CFCMOVNLE	T	T	T
CFCMOVNO	T
CFCMOVNP				T
CFCMOVNS		T
CFCMOVNZ			T
CFCMOVO	T
CFCMOVP				T
CFCMOVS		T
CFCMOVZ			T

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: APX-EVEX-CFCMOV

Attributes

What else XED records about the forms. How to read.

Memory forms: memory fault suppression

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`APX_F_N3` APX	APX_F + APX_NCI_NDD_NF `CPUID.(EAX=07H,ECX=1):EDX[21]` APX_F `CPUID.(EAX=29H,ECX=0):EBX[0]` APX_NCI_NDD_NF	Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions