CLC instruction (General-purpose)

CLC clears the carry flag and leaves every other flag and register as it was. With STC, which sets CF, and CMC, which inverts it, it is one of three instructions that work on CF alone; CLD and STD do the same for the direction flag.

Uses

Starting a carry chain. An ADC with CF clear is an ADD, so a loop whose body is all ADC can handle the first word like the others when CF is cleared before it. The loop must then count with an instruction that leaves CF alone, such as DEC or LOOP.
Returning a yes or no. An assembly routine can report its result in CF, with CLC or STC just before its RET, and the caller tests it with JC, JNC or SETC. From C, GCC’s and Clang’s flag output operands read CF straight out of inline assembly: an asm block that runs stc with the output constraint "=@ccc" compiles, at -O2 in GCC 14 and Clang 23, to the STC and a SETC (Clang prints it as SETB), with no PUSHF or LAHF.
Before a rotate through CF. RCL and RCR shift CF in, so clearing it first makes them shift a zero in.

Compiled C seldom needs CLC, since the compilers fold a known carry into the arithmetic: for a + (b < c) on unsigned numbers, both emit cmp rsi, rdx and adc rax, 0, the comparison itself setting CF.

Partial flag writes

Intel’s optimization manual names STC among the instructions that write only part of the flags register; CLC and CMC do the same. On processors before Sandy Bridge, an instruction that follows such a write and depends on the flags may stall; from Sandy Bridge on, the cost is an extra micro-op instead (Section 3.5.2.5). The manual still recommends using them sparingly before instructions whose flag writes depend on their operands, such as shifts by CL. The instruction table of AMD’s Zen 5 guide lists CLC, STC and CMC each as one macro-op.

Forms

Every encoding of CLC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CLC` CLC	`F8`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CLC`
Sandy Bridge, Haswell, Broadwell	1 / 0.25
Skylake, Skylake-SP, Ice Lake	1 / 0.17
Alder Lake, Sapphire Rapids, Lunar Lake	1 / 0
Bonnell	1 / 0.5p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

cf = 0

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CLC`
`RFLAGS`	implicit	write

Flags

0 cleared; blank: not affected. How to read.

CF
All forms
0

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Uses#

Partial flag writes#