CLD instruction (General-purpose)

CLD clears the direction flag, DF, so that the string instructions, MOVS, STOS, LODS, CMPS, SCAS, INS and OUTS, step RSI and RDI up after each element. It changes no other flag. STD sets DF. Zen 5 cleared bit 10 in its two recorded cases that had it set and changed nothing in the four that did not.

When it is needed

The System V and Microsoft x64 calling conventions require DF clear at every call and return (see the registers), so ordinary code never needs CLD: GCC 14 at -O2 copies and clears a 512-byte struct with REP MOVS and REP STOS of quadwords and no CLD. CLD belongs where that guarantee does not hold yet or was broken:

after a sequence that ran STD for a backward copy, before the code calls or returns;
at entry points that the convention does not cover, such as a handler entered through an interrupt or trap gate: delivery clears TF, NT, RF and VM, and IF for an interrupt gate, but leaves DF as the interrupted code had it (Intel’s Volume 3, Section 7.12.1.3);
in inline assembly that wants to be safe whatever its caller did: glibc’s <sys/io.h> puts a CLD before its REP INS and REP OUTS, so insw(port, buf, n) compiles to cld and rep insw in both compilers.

GCC 14 also has the option -mcld, which makes it emit CLD in the functions where it generates string instructions: with it, the struct copy above becomes a CLD followed by the REP MOVS. Clang 23 does not accept the option.

Cost

The instruction table of AMD’s Zen 5 guide lists CLD as microcoded, as it does STD, while CLC and STC are single macro-ops. A CLD that is not needed is thus not free on Zen 5.

Forms

Every encoding of CLD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CLD` CLD	`FC`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CLD`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	3 / 1p0156
Alder Lake, Sapphire Rapids	3 / 0.5p0 p1 p5 p6 p11
Lunar Lake	3 / 0.33p012345
Bonnell	3 / 1.5p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

df = 0                           # string instructions step rSI and rDI up

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CLD`
`RFLAGS`	implicit	write

Flags

0 cleared; blank: not affected. How to read.

DF
All forms
0

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction in some cases

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

When it is needed#

Cost#