x86-64.net

Instruction

CLDEMOTE

Hints that the cache line holding a byte of memory should move from the core's caches to a more distant level, where other cores reach it sooner.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of CLDEMOTE that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CLDEMOTE m8 CLDEMOTE_MEMu8NP 0F 1C /0CLDEMOTE

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CLDEMOTE

CLDEMOTE
CPUID.(EAX=07H,ECX=0):ECX[25] CLDEMOTE

Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Tremont, Snow Ridge, Sierra Forest, Clearwater Forest

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.