CLFLUSH

CLFLUSH removes the cache line holding a byte from every cache in the system, writing it back to memory first if a cache holds it modified. Memory keeps its value; what changes is where the data lives, which matters to code that shares memory with devices that do not snoop the caches, and to code that must make data durable in persistent memory, for which Intel’s optimization manual recommends CLFLUSHOPT, or CLWB where the data will be used again (Section 12.4). CLFLUSHOPT and CLWB are the faster and the non-evicting variants.

Not a hint#

Unlike a prefetch, CLFLUSH is checked like a 1-byte load: user code may run it, but only on memory it can read. On Zen 5 it ran without a fault on a mapped line, and raised #PF for an unmapped address near 0 and for a kernel address, where PREFETCHT0 went on without a fault. Like a load, it sets the page’s accessed bit but not its dirty bit. The size of a line is in CPUID leaf 1, EBX bits 15:8, in units of 8 bytes, typically 64 bytes. A buffer is flushed line by line; _mm_clflush(p) in a loop that steps by 64 compiles to one CLFLUSH per line in GCC 14 and Clang 23.

Ordering differs between vendors#

Intel’s manual orders CLFLUSH with every write, every other CLFLUSH, locked instructions and fences, but not with CLFLUSHOPT or CLWB; its optimization manual adds that the MFENCE older manuals required after CLFLUSH is no longer needed (Section 9.4.6). AMD’s manual is weaker: on processors with CLFLUSHOPT, such as Zen 5, CLFLUSH is ordered with writes, CLFLUSH and CLFLUSHOPT only for the same line, and with fences and locked instructions; on older ones it is weakly ordered and needs MFENCE before and after. Loads and prefetches can bring a line back at any time on both. Code meant for either vendor therefore puts MFENCE after a flush loop, as both compilers emit for _mm_mfence().

Speed#

Intel’s manual finds CLFLUSHOPT with a final SFENCE much faster than CLFLUSH for buffers larger than a few KB, and advises CLFLUSH in smaller chunks where only it is available (Section 9.4.7). The instruction table of AMD’s Zen 5 guide lists CLFLUSH as microcoded and CLFLUSHOPT as one macro-op.

CLFLUSH has its own CPUID bit, CLFSH (leaf 1, EDX bit 19), which every x86-64 processor sets.

In the optimization guide

What the optimization guide says about CLFLUSH, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

• Non-temporal stores and fences: CLFLUSHOPT flushes lines as CLFLUSH does but with less ordering, so a series of them runs much faster.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src.address                  # DS:, or a segment prefix's base
if not canonical(a):
    fault(GP, 0)                 # #SS(0) through RSP or RBP
if not readable(a):
    fault(PF)                    # the checks of a 1-byte read, which
                                 # an execute-only segment passes; the
                                 # A bit of the page is set, not D
# the line leaves every cache of the coherence domain, written back
# to memory first where a cache holds it modified; memory keeps its
# value. Ordered with writes, fences, locked instructions and other
# CLFLUSHes, not with CLFLUSHOPT or CLWB (Intel's manual). AMD's
# orders it with writes, CLFLUSHes and CLFLUSHOPTs only to the same
# line where CLFLUSHOPT exists, and weakly where it does not

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.