CLFLUSHOPT

CLFLUSHOPT does what CLFLUSH does: it removes the cache line holding a byte from every cache, writing it back first if it was modified, with the checks of a 1-byte read. Zen 5 ran it without a fault on a mapped line and raised #PF for an unmapped address near 0 and for a kernel address. The difference is ordering: a CLFLUSHOPT need not wait for flushes of other lines, so a loop can have many in flight, and a fence afterwards says when they are done. Its encoding is CLFLUSH’s with a 66 prefix, 66 0F AE /7, and its CPUID bit is leaf 7, EBX bit 23.

The fence is the program’s job#

Both vendors order CLFLUSHOPT with fences, locked instructions and earlier stores to the same line, and leave it free to pass stores to other lines. Code that must know the data has reached memory, such as a write to persistent memory, therefore writes, flushes each line and ends with SFENCE, the sequence Intel’s optimization manual gives (Section 9.4.7, Example 9-2); MFENCE also works. Without the fence, a later store, for example the one that marks a record as committed, can become visible first.

The manuals differ on flushes of the same line. Intel’s instruction reference leaves CLFLUSHOPT unordered with other CLFLUSHOPTs and with CLFLUSH, making no exception for the same line; Intel’s optimization manual and AMD’s manual order them when they name the same line. Intel’s reference also leaves it unordered with later stores to the line it flushes.

From C#

_mm_clflushopt(p) needs the feature enabled: with -mclflushopt, or -march=skylake, znver1 and later. With plain -O2 or -march=x86-64-v4, GCC 14 and Clang 23 reject the call. A loop that steps by 64 and ends with _mm_sfence() compiles to one CLFLUSHOPT per line and an SFENCE; GCC unrolls it by two.

Which flush to choose#

Intel’s optimization manual finds CLFLUSHOPT up to nine times faster than CLFLUSH for large buffers in a single thread on Skylake and advises it wherever it exists (Section 9.4.7). Where the data will be read again soon, CLWB writes the line back and may keep it cached (Section 12.4). AMD’s Zen 5 guide lists CLFLUSHOPT as one macro-op, where CLFLUSH is microcoded.

In the optimization guide

What the optimization guide says about CLFLUSHOPT, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

• Non-temporal stores and fences: CLFLUSHOPT flushes lines as CLFLUSH does but with less ordering, so a series of them runs much faster.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src.address                  # DS:, or a segment prefix's base
if not canonical(a):
    fault(GP, 0)                 # #SS(0) through RSP or RBP
if not readable(a):
    fault(PF)                    # the checks of a 1-byte read
# as CLFLUSH, but ordered only with fences, locked instructions and
# earlier writes to the same line, so that several can be in flight
# (an SFENCE orders them)

Operands

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

memory operand only names cache lines

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CLFLUSHOPT, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.