CLI instruction (General-purpose)

CLI clears IF, the interrupt flag, so that the logical processor stops accepting maskable external interrupts until IF is set again by STI, POPF or IRET. Exceptions, NMIs and the software interrupts of INT still come through: IF holds off only interrupts from devices and the interrupt controller. A kernel uses CLI around code that an interrupt handler on the same processor must not run in the middle of, such as an update of that processor’s own data. IF belongs to one logical processor, so CLI does nothing to keep other processors out of shared data; that takes a lock.

Saving IF rather than clearing it

Code that may itself run with interrupts already off saves RFLAGS with PUSHF before the CLI and puts it back with POPF afterwards, so that IF returns to what it was instead of being set by an STI the caller did not expect.

Who may run it

CLI is I/O-sensitive, like IN and OUT: it clears IF when CPL is at most IOPL. Otherwise, at CPL 3 with CR4.PVI set (protected-mode virtual interrupts, which Intel’s manual says include 64-bit mode), it clears VIF, bit 19, instead and leaves IF alone, so that an operating system can track a virtual interrupt flag for code that expects to run CLI. In any other case it raises #GP(0); the two vendors’ manuals agree on this. The probe runs at CPL 3 with IOPL 0, and Zen 5 raised #GP there in each of its three recorded cases, with RFLAGS unchanged.

POPF differs: at the same privilege it does not fault but leaves IF as it was, so code cannot rely on a POPF to have turned interrupts off.

Kin

User interrupts, a separate mechanism, have their own flag, UIF, with CLUI and STUI as their CLI and STI. The instruction table of AMD’s Zen 5 guide lists CLI as microcoded.

Forms

Every encoding of CLI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CLI` CLI	`FA`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CLI`
Sandy Bridge	5 / 2p15
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	100 / 0.25p0156
Alder Lake, Sapphire Rapids	100 / 1p016
Lunar Lake	100 / 1p0124
Bonnell	100 / 0.5p01
Silvermont	100 / 1FPC0
Piledriver	100 / 0.5EX0 EX1
Zen, Zen 2	100 / 0.25
Zen 3, Zen 4	100 / 25ALU0 ALU1 ALU2 ALU3
Jaguar	100 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL <= iopl:
    if_ = 0                      # maskable interrupts held off
elif CPL == 3 and cr4 >> 1 & 1:  # CR4.PVI: protected-mode virtual
    vif = 0                      # interrupts, VIF in IF's place
else:
    fault(GP, 0)                 # as in the probe's cases: CPL 3, IOPL 0

Run on AMD Zen 5 (EPYC 9645): 3 cases. Every one raised an exception, at CPL 3, where the probe runs.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CLI`
`RFLAGS`	implicit	read, write

Flags

T tested, M modified; blank: not affected. How to read.

IF	IOPL	VIF
All forms
M	T	M

Attributes

What else XED records about the forms. How to read.

All forms: may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Saving IF rather than clearing it#

Who may run it#

Kin#