CLTS

CLTS clears TS, bit 3 of CR0, and nothing else. TS exists for lazy saving of the floating-point state: while it is set, the first x87, MMX, SSE or AVX instruction raises #NM, the device-not-available exception, before it runs, and so do FXSAVE and the XSAVE family. An operating system that switches tasks without saving the vector registers sets TS; if the new task never touches them, nothing is saved at all, and if it does, the #NM handler saves the previous owner’s state, loads the new one and runs CLTS so that the instruction can be retried without another fault.

Where TS comes from#

The 32-bit task switch of protected mode sets TS on its own. That mechanism does not exist in long mode, so in 64-bit mode TS is set only by software, with MOV to CR0 or LMSW. CLTS is the one way to clear it without rewriting the whole of CR0, which needs a read of CR0 with MOV first.

What TS does not stop#

Intel’s Volume 3 lists the instructions that run despite TS because they do not touch that state: PAUSE, the prefetches, SFENCE, LFENCE, MFENCE, MOVNTI, CLFLUSH, CRC32 and POPCNT. With MP clear, WAIT and FWAIT run too. With CR0.EM set, TS changes nothing, since EM’s own rules then govern the x87, MMX and SSE instructions.

Privilege and virtualization#

CLTS runs only at CPL 0, and in real mode, so that start-up code can use it before protected mode is entered; elsewhere it raises #GP(0). At CPL 3, Zen 5 raised #GP in both recorded cases, with RFLAGS left alone. Under VMX, the CR0 guest/host mask and read shadow decide: a hypervisor that owns TS can make CLTS exit, let it complete without changing the guest’s view, or let it clear TS as usual. Neither GCC 14 nor Clang 23 has an intrinsic for it: C code needs inline assembly. AMD’s Zen 5 guide lists CLTS as microcoded.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if CPL > 0:
    fault(GP, 0)
cr0 = cr0 & ~8                   # TS, bit 3, which a task switch sets
                                 # so that the next x87, MMX or SSE
                                 # instruction raises #NM

Operands

None: XED lists no operands for this form.

Flags

None: XED records no flag that the forms test or change.

Attributes

What else XED records about the forms. How to read.

All forms

privileged: CPL 0 only; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More System instructions

• ARPL
• HLT
• INVD
• INVLPG
• LAR
• LGDT
• LIDT
• LLDT
• LMSW
• LSL
• LTR
• RDMSR
• RDPMC
• RDTSC
• RSM
• SGDT
• SIDT
• SLDT
• SMSW
• STR
• SWAPGS
• VERR
• VERW
• WBINVD
• WRMSR