Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

CLUI clears the user-interrupt flag, UIF, and holds back user interrupts from the next instruction boundary on: unlike CLI, it needs no privilege, so a program can protect its own critical sections from its own user-interrupt handler, the way a kernel does with IF. STUI sets the flag again and TESTUI reads it.

What a held interrupt does

CLUI does not discard anything. A user interrupt that arrives while UIF is clear stays recorded as a request, and requests posted for the thread by SENDUIPI keep accumulating, one bit per vector; once UIF is set again, the processor delivers the highest pending vector at the next instruction boundary. Several requests with the same vector merge into one bit, so a handler cannot count deliveries to count events.

Delivery itself clears UIF before the handler’s first instruction, so a handler does not need a CLUI to keep from being interrupted by the next user interrupt.

In compiled code

GCC 14 and Clang 23 with -muintr at -O2 compile _clui() to clui. A section that must work whether or not user interrupts were enabled on entry reads the flag with _testui() first and sets it again only if it was set; both compilers made TESTUI, a SETcc of CF, CLUI, the protected code and a test that branches around the STUI.

Where it runs

CLUI exists only in 64-bit mode, needs UINTR (CPUID leaf 7, EDX bit 5) and CR4.UINTR, and raises #UD otherwise, inside an enclave or with a LOCK prefix; in a TSX transaction it aborts the transaction as CLI would. Its bytes, F3 0F 01 EE, are those of RDPKRU with an F3 prefix; the probe does not run them, as the Operation section says, so the site has no Zen 5 result for CLUI.

Forms

Every encoding of CLUI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CLUI 64-bit mode only CLUIF3 0F 01 EEUINTR

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelCLUI
Sapphire Rapids100 / 0.25p0156

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cr4 >> 25 & 1:            # CR4.UINTR; clear without UINTR
    fault(UD)
uif = 0                          # at once: no user interrupt is
                                 # delivered after it

Not run on a processor: its bytes are RDPKRU's with an F3 prefix, which a processor without UINTR may run as RDPKRU, so that a case would not record CLUI; and no processor at hand has UINTR.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
CLUI 64-bit mode only
UIFimplicitwrite

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CLUI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_clui void _clui(void)

CLUI Legacy -muintr

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
UINTR

UINTR
CPUID.(EAX=07H,ECX=0):EDX[5] UINTR

Arrow Lake, Panther Lake, Nova Lake, Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest

More UINTR instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-153 (CLUI)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (325384-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.