x86-64.net

Instruction

CLZERO

Writes zeros to the whole cache line that contains the address in rAX.

An AMD extension: Intel processors do not have this instruction.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of CLZERO that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CLZERO CLZERO0F 01 FCCLZERO

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelCLZERO
Zen4 / 0.5AGU0 AGU1
Zen 24 / 0.33AGU0 AGU1 AGU2
Zen 3, Zen 45 / 0.33AGU0 AGU1 AGU2 LSU Load

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = low(rax, ASIZE) & ~63        # RAX, or EAX with a 67 prefix: the
                                 # line that holds it, 64 bytes on
                                 # Zen 5 (8 * CPUID 1 EBX[15:8])
if not canonical(a):
    fault(GP, 0)
if not writable(a):
    fault(PF)                    # the checks of a store of the line
for i in range(8):
    store(a + 8 * i, 64, 0)      # every byte of the line 0
# with a hint that the line need not stay in the caches, and weakly
# ordered with other stores: an SFENCE orders it

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
CLZERO
rAXimplicitread

Flags

None: XED records no flag that the forms test or change.

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CLZERO, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_clzero void _mm_clzero(void *__line)

CLZERO Legacy -mclzero

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
CLZERO

CLZERO
CPUID.80000008H:EBX[0] CLZERO

Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.38, July 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.