CMC instruction (General-purpose)

CMC inverts the carry flag and leaves the other flags alone. Unlike CLC and STC, whose result is fixed, it reads CF, so it waits for the instruction that last wrote the flag.

Turning a borrow around

After a CMP or SUB of unsigned numbers, CF is the borrow: 1 when the first operand is below the second. CMC turns that into its opposite, 1 when the first is above or equal, ready for an ADC, an SBB or a rotate through CF.

Compilers get the same effect without it. For a + (b >= c) on unsigned longs, GCC 14 and Clang 23 at -O2 emit cmp rsi, rdx and sbb rax, -1: subtracting -1 and the borrow adds 1 - CF, which is 1 exactly when b >= c. a - (b >= c) becomes adc rax, -1 the same way. The operation the program wants decides between ADC and SBB, and the constant absorbs the inversion, so neither compiler needed a CMC in these cases.

Other points

Only CF. CMC changes no other flag, so a JZ or JS after it still sees the flags of the comparison before it.
No CMC for other flags. x86 has no instruction that inverts ZF or OF alone; the condition codes of Jcc, SETcc and CMOVcc come in pairs instead, each with its negation.

Intel’s optimization manual explains that instructions writing only part of the flags, such as STC, can stall a following instruction that depends on the flags on processors before Sandy Bridge, and cost an extra micro-op since (Section 3.5.2.5); CMC is such an instruction. The instruction table of AMD’s Zen 5 guide lists CMC as one macro-op with a latency of one cycle.

Forms

Every encoding of CMC that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CMC` CMC	`F5`	Base instruction set

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`CMC`
Sandy Bridge	1 / 0.33p015
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake	1 / 0.25p0156
Alder Lake, Sapphire Rapids	1 / 0.2p0 p1 p5 p6 p11
Lunar Lake	1 / 0.33p135
Bonnell	1 / 0.5p01
Silvermont	1 / 0.5IEC0 IEC1
Piledriver	1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 4	1 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar	1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

cf = cf ^ 1

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CMC`
`RFLAGS`	implicit	read, write

Flags

T tested, M modified; blank: not affected. How to read.

CF
All forms
TM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`I86` General-purpose System	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Turning a borrow around#

Other points#