Instruction
CMOVcc
Copies the source to a register if a condition on the flags holds; APX adds a three-operand form that picks one of two sources.
- Extensions
- Mnemonics
- CMOVO, CMOVNO, CMOVB, CMOVC, CMOVNAE, CMOVNB, CMOVNC, CMOVAE, CMOVZ, CMOVE, CMOVNZ, CMOVNE, CMOVBE, CMOVNA, CMOVNBE, CMOVA, CMOVS, CMOVNS, CMOVP, CMOVPE, CMOVNP, CMOVPO, CMOVL, CMOVNGE, CMOVNL, CMOVGE, CMOVLE, CMOVNG, CMOVNLE, CMOVG
- Forms
- 4 (2 Legacy, 2 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
CMOVcc r16/32/64, m16/32/64
CMOVcc_GPRv_MEMv | 0F 40+cc /r | CMOV |
CMOVcc r16/32/64, r16/32/64
CMOVcc_GPRv_GPRv | 0F 40+cc /r | CMOV |
CMOVcc r16/32/64, r16/32/64, r16/32/64 NDD
CMOVcc_GPRv_GPRv_GPRv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 | APX_F + APX_NCI_NDD_NF |
CMOVcc r16/32/64, r16/32/64, m16/32/64 NDD
CMOVcc_GPRv_GPRv_MEMv_APX_N3 | EVEX.LLZ.NP.MAP4.SCALABLE 40+cc /r ND=1 | APX_F + APX_NCI_NDD_NF |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
CMOV | CMOV | Every x86-64 processor in XED’s model |
APX_F_N3 | APX_F + APX_NCI_NDD_NF | Nova Lake, Diamond Rapids |
More APX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.