CMP

CMP a, b computes a - b, sets the flags as SUB would and throws the difference away. Its meaning comes from the instruction that reads the flags next, a Jcc, SETcc or CMOVcc, whose condition code says both which relation is tested and whether a and b are signed:

The same flags serve both columns. CF is the borrow out of the subtraction, so B (CF = 1) holds exactly when a < b as unsigned numbers. For signed numbers the sign of the difference is right unless the subtraction overflowed, and L tests SF XOR OF to correct for that. The manuals keep the words apart in the same way: “below” and “above” for unsigned, “less” and “greater” for signed.

Operand order#

In Intel syntax the first operand is the minuend: cmp rdi, rsi then jl jumps when RDI < RSI. AT&T syntax writes the operands the other way round, so the same instruction is cmpq %rsi, %rdi followed by jl, which is what GCC 14 at -O2 prints for if (a < b) with a in RDI. Reading cmp in AT&T as “compare the first with the second” gets every condition but E and NE backwards.

Constants#

An immediate is 8 or 32 bits, sign-extended to the operand size; no form takes a 64-bit immediate. Comparing a 64-bit register with 0x123456789 therefore takes two instructions in both GCC 14 and Clang 23: movabs rax, 0x123456789 and cmp rdi, rax. A comparison with zero needs no immediate at all: compilers use TEST with the register twice, which is shorter and sets every condition the same way.

APX adds CCMPscc, which compares only if an earlier condition holds, so that a == 1 && b > c needs no branch between its terms.

In the optimization guide

What the optimization guide says about CMP, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Front end

• Macro-fusion: Intel’s cores since Sandy Bridge (Skylake) fuse test and and with any conditional branch; cmp, add and sub with branches on the equal, unsigned and signed comparisons, but not on the sign, parity or overflow flag alone; and inc and dec only with branches on equality and the signed comparisons.
• Macro-fusion: AMD’s Zen 3 to Zen 5 fuse more: cmp, test, add, sub, and, or, xor, inc and dec with any conditional branch, except that on Zen 3 and Zen 4 inc and dec do not fuse with a branch that reads the carry flag, which Intel’s cores do not fuse either (Zen 5, Zen 4, Zen 3). sources differ
• Macro-fusion: With a memory operand, Intel’s Sandy Bridge to Skylake do not fuse an instruction that also has an immediate, while AMD’s Zen 3 and Zen 4 still fuse cmp and test unless a displacement comes with the immediate or the address is relative to RIP. sources differ
• Macro-fusion: On Intel’s cores the choice of instruction decides fusion more often, so Intel prefers test to cmp for a comparison with zero, as test fuses with every condition.

Out of order

• Zeroing and dependency-breaking idioms: AMD’s cores recognize two more: cmp eax, eax, which takes no cycle, and sbb eax, eax, which turns the carry flag into 0 or all ones in one cycle without waiting for EAX.

Bulldozer to Excavator

• Branches: A cmp or test directly followed by a conditional branch fuses into one op, unless the compare uses a RIP-relative address or has a displacement as well as an immediate; no other instruction fuses. sources differ

Haswell and Broadwell

• Front end: CMP, ADD and SUB fuse with a following conditional jump that tests carry, zero, or a signed or unsigned comparison; INC and DEC only with one that tests zero or a signed comparison; TEST and AND with any.

Ice Lake to Rocket Lake

• Front end: A cmp, add, sub, inc or dec fuses with a following jump on zero, carry or an unsigned or signed comparison, and test or and with any conditional jump; or, xor, adc, sbb, shifts and js, jo and jp never fuse.

Sandy Bridge and Ivy Bridge

• Front end: Sandy Bridge widens macro-fusion from Nehalem’s CMP and TEST to also fuse ADD, SUB, AND, INC and DEC with a following conditional branch, fusing when the first instruction’s first operand is a register and its second operand, if any, is an immediate, a register or memory that is not RIP-relative; the pair does not fuse only when the first instruction ends on the last byte of a 64-byte line and the branch begins the next line’s first byte.

Skylake to Cooper Lake

• Front end: test and and fuse with any following conditional jump; cmp, add and sub with the jumps on equality and on the unsigned and signed comparisons, but not with js, jp or jo and their inverses; inc and dec only with those on equality and the signed comparisons.

Zen and Zen+

• Integer execution: Only a cmp or test directly followed by a conditional branch fuses into one macro-op, and not when it has a displacement together with an immediate, or an address relative to RIP; no other arithmetic or logic instruction fuses.

Zen 2

• Integer execution: Only a cmp or test followed by a conditional branch fuses into one macro-op, not one with a displacement together with an immediate or an address relative to RIP; the arithmetic and logic instructions that fuse on Zen 3 do not.

Zen 3

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag, and jrcxz never fuses.

Zen 4

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, unless it carries a displacement together with an immediate, addresses relative to RIP or makes the pair longer than 15 bytes; inc and dec do not fuse with a branch on the carry flag.

Zen 5

• Integer execution: A cmp, test, add, sub, inc, dec, and, or or xor followed by a conditional branch becomes one macro-op, also with a memory operand, within limits on the sizes of its displacement and immediate.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

b = sext(src2)                   # an immediate is sign-extended to OSIZE
flags = sub_flags(src1, b)       # as SUB, but nothing is written

Operands

Flags

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More General-purpose instructions

• AAS
• ADC
• ADD
• AND
• BOUND
• BSF
• BSR
• BSWAP
• BT
• BTC
• BTR
• BTS
• CALL
• CBW
• CDQ
• CDQE
• CLC
• CLD
• CLI
• CMC
• CMPS
• CMPXCHG
• CMPXCHG8B
• CPUID
• CQO
• CWD
• CWDE
• DAA
• DAS
• DEC
• DIV
• ENTER
• IDIV
• IMUL
• IN
• INC
• INS
• INT
• INT1
• INT3

All 109 General-purpose instructions