x86-64.net

Instruction

CMPccXADD

Atomically compares memory with a register, adds a second register to memory if the condition holds, and returns the old value in the first.

Extensions
Mnemonics
CMPOXADD, CMPNOXADD, CMPBXADD, CMPCXADD, CMPNAEXADD, CMPNBXADD, CMPNCXADD, CMPAEXADD, CMPZXADD, CMPEXADD, CMPNZXADD, CMPNEXADD, CMPBEXADD, CMPNAXADD, CMPNBEXADD, CMPAXADD, CMPSXADD, CMPNSXADD, CMPPXADD, CMPPEXADD, CMPNPXADD, CMPPOXADD, CMPLXADD, CMPNGEXADD, CMPNLXADD, CMPGEXADD, CMPLEXADD, CMPNGXADD, CMPNLEXADD, CMPGXADD
Forms
4 (2 VEX, 2 EVEX)
Data
Intel XED v2026.08.23

CMPccXADD m, r1, r2 performs these steps as one locked operation:

  1. Read the memory value and compare it with r1, setting the flags as CMP would (memory minus r1).
  2. If the condition cc holds for those flags, write the memory value plus r2 back to memory; otherwise leave memory unchanged.
  3. Put the original memory value in r1.

Without it, a conditional atomic update such as “increment the counter unless it has reached the limit” needs a loop around LOCK CMPXCHG that retries whenever another thread changed the value in between. CMPccXADD always completes in one step and returns the old value and the flags of the comparison, so the caller knows whether the addition happened. The lock is implicit, a LOCK prefix is not allowed, and the memory operand cannot be a register.

Forms

Every encoding of CMPccXADD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CMPccXADD m32, r32, r32 64-bit mode only CMPccXADD_MEMu32_GPR32u32_GPR32u32VEX.LZ.66.0F38.W0 E0+cc /rCMPCCXADD
CMPccXADD m64, r64, r64 64-bit mode only CMPccXADD_MEMu64_GPR64u64_GPR64u64VEX.LZ.66.0F38.W1 E0+cc /rCMPCCXADD
CMPccXADD m32, r32, r32 CMPccXADD_MEMu32_GPR32u32_GPR32u32_APXEVEX.LLZ.66.0F38.W0 E0+cc /rAPX_F + CMPCCXADD
CMPccXADD m64, r64, r64 CMPccXADD_MEMu64_GPR64u64_GPR64u64_APXEVEX.LLZ.66.0F38.W1 E0+cc /rAPX_F + CMPCCXADD

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPccXADD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_cmpccxadd_epi32 int _cmpccxadd_epi32(void *__A, int __B, int __C, const int __D)

CMPccXADD m32, r32, r32 VEX.LZ -mcmpccxadd

_cmpccxadd_epi64 long long _cmpccxadd_epi64(long long *__A, long long __B, long long __C, const int __D)

CMPccXADD m64, r64, r64 VEX.LZ -mcmpccxadd

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CMPCCXADD

CMPCCXADD
CPUID.(EAX=07H,ECX=1):EAX[7] CMPCCXADD

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest
APX_F_CMPCCXADD

APX_F + CMPCCXADD
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=07H,ECX=1):EAX[7] CMPCCXADD

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.