CMPccXADD

CMPccXADD m, r1, r2 performs these steps as one locked operation:

1. Read the memory value and compare it with r1, setting the flags as CMP would (memory minus r1).
2. If the condition cc holds for those flags, write the memory value plus r2 back to memory; otherwise leave memory unchanged.
3. Put the original memory value in r1.

Without it, a conditional atomic update such as “increment the counter unless it has reached the limit” needs a loop around LOCK CMPXCHG that retries whenever another thread changed the value in between. CMPccXADD always completes in one step and returns the old value and the flags of the comparison, so the caller knows whether the addition happened. The lock is implicit, a LOCK prefix is not allowed, and the memory operand cannot be a register.

XED marks the memory operand as needing natural alignment, four bytes for m32 and eight for m64, as the attributes below show. Intel’s manual of September 2026 (325383-093) has no such rule. Of the exceptions of CMPccXADD (Exceptions Type 14, Table 2-31), only #AC(0) concerns alignment: an unaligned operand raises it when alignment checking is enabled at CPL 3. #GP(0) comes only from a non-canonical address. As with any locked access, an operand that spans two cache lines needs a bus lock, which system software can turn into #AC(0) with split-lock disable (Volume 3A, Section 11.1.2.3).

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

old = dest.read()                # one locked read-modify-write
f = sub_flags(old, src1)         # as CMP dest, src1
if cond(CC, f):                  # the condition on these new flags
    dest.write(old + src2)
else:
    dest.write(old)              # memory is written back all the same
src1.write(old)                  # whatever the condition
flags = f

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-14

EVEX forms

APX-EVEX-CMPCCXADD

Attributes

What else XED records about the forms. How to read.

All forms

always atomic

CMPccXADD m32, r32, r32 64-bit mode only

4-byte aligned memory operand

CMPccXADD m64, r64, r64 64-bit mode only

8-byte aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPccXADD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CRC32
• CTESTscc
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions