CMPPD

CMPPD is SSE2’s packed compare of doubles: it tests both pairs of elements under one predicate and writes all ones or zero to each quadword of the destination. The predicate is one of the eight of CMPPS, whose page gives them with their treatment of NaNs; assemblers also accept names such as CMPLTPD and CMPUNORDPD, which supply the immediate. Intel’s manual has the legacy form read only bits 2:0 of the immediate, against bits 4:0 for VCMPPD, and on Zen 5 the recorded cmppd xmm0, xmmword ptr [mem], 0x13 acted as predicate 3, unordered and quiet: all ones for two quiet NaNs, zero for 1.0 against 2^-53, and no flag set in MXCSR, where VCMPPD’s predicate 13h would have raised the invalid-operation flag for the quiet NaNs.

Masks in compiled code#

The masks feed logic and integer instructions. In our builds at -O2 for the SSE2 baseline, over arrays of 1024 doubles (GCC 14 keeps a loop whose count is known only at run time scalar, with COMISD):

• isnan(a[i]) is cmpunordpd x, x, the element compared with itself, and replacing NaNs with zero is CMPORDPD on itself followed by an ANDPD.
• A select such as a[i] <= b[i] ? 1.0 : r[i] is the mask, ANDPD, ANDNPD and ORPD, or one BLENDVPD with -march=x86-64-v2.
• Counting the elements where a[i] < b[i], Clang 23 subtracts each mask, which is -1 as an integer, from a running sum with PSUBD; GCC 14 ANDs the masks with 1 and adds.

There are no greater-than predicates: _mm_cmpgt_pd and _mm_cmpge_pd compile to CMPLTPD and CMPLEPD with the operands swapped, which costs a MOVAPD when the result must end up in the first operand. Clang 23 accepts the generic _mm_cmp_pd with predicates 0 to 7 for plain SSE2 and emits CMPPD; predicates above 7 need AVX, and GCC 14 declares _mm_cmp_pd for AVX only.

AMD’s latency spreadsheet for Zen 5 gives CMPPD two cycles, on pipes FP2 and FP3. The legacy form keeps bits 255:128 of its register (see mixing SSE and AVX), and its memory operand must be aligned to 16 bytes.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    a = xmm1.f64[i]
    b = src2.f64[i]
    if fcmp(imm8 & 7, a, b):
        xmm1.q[i] = -1
    else:
        xmm1.q[i] = 0
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPPD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE2 instructions

• ADDPD
• ADDSD
• ANDNPD
• ANDPD
• CMPSD
• COMISD
• CVTDQ2PD
• CVTDQ2PS
• CVTPD2DQ
• CVTPD2PI
• CVTPD2PS
• CVTPI2PD
• CVTPS2DQ
• CVTPS2PD
• CVTSD2SI
• CVTSD2SS
• CVTSI2SD
• CVTSS2SD
• CVTTPD2DQ
• CVTTPD2PI
• CVTTPS2DQ
• CVTTSD2SI
• DIVPD
• DIVSD
• LFENCE
• MASKMOVDQU
• MAXPD
• MAXSD
• MFENCE
• MINPD
• MINSD
• MOVAPD
• MOVD
• MOVDQ2Q
• MOVDQA
• MOVDQU
• MOVHPD
• MOVLPD
• MOVMSKPD
• MOVNTDQ

All 124 SSE2 instructions