CMPPS

CMPPS compares the four singles of its first operand with those of the second and replaces each element of the first with all ones where the predicate holds and zero where it does not. The immediate chooses the predicate, and the legacy form reads only its bits 2:0, which give the eight below; a, the first operand, stands on the left of each relation. VCMPPS adds 24 predicates with bits 3 and 4 and can write a mask register; CMPPD, CMPSS and CMPSD use the same eight codes for doubles and single elements.

The eight predicates#

A signaling NaN sets IE under every predicate. The negations are not the reversed relations: NLT differs from “greater or equal” exactly where a NaN makes the result true. There is no greater-than code: _mm_cmpgt_ps(a, b) compiles in our builds to cmpltps xmm1, xmm0, b first, and a MOVAPS back to XMM0, as the result replaces the first operand. The other legacy traits apply too: bits 128 and up stay (see SSE and AVX) and a memory operand must be aligned to 16 bytes.

On Zen 5#

• cmpps xmm4, xmm4, 0x8 acted as predicate 0: a quiet NaN compared unequal to itself and set no flag, where VCMPPS’s predicate 8 would have returned true.
• cmpps xmm7, xmm11, 0x3, unordered, set DE for denormal inputs as well as IE for a signaling NaN; cmpps xmm8, xmm15, 0x7, ordered, set DE alone.
• With IE unmasked, cmpps xmm0, xmm13, 0x5 set IE, raised #XM for a signaling NaN and left XMM0 as it was.

In baseline code#

In our builds at -O2 for the default target, Clang 23 vectorizes compares over float arrays with CMPPS: < as CMPLTPS, > as CMPLTPS with the operands swapped, >= as CMPLEPS swapped, == as CMPEQPS, != as CMPNEQPS, and isnan(x) and isunordered as CMPUNORDPS. A select between two values adds ANDPS, ANDNPS and ORPS, or one BLENDVPS with -march=x86-64-v2. Like VCMPPS’s loops, isless used the signaling CMPLTPS. GCC 14 kept the same loops scalar, with COMISS and UCOMISS.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    a = xmm1.f32[i]
    b = src2.f32[i]
    if fcmp(imm8 & 7, a, b):
        xmm1.d[i] = -1
    else:
        xmm1.d[i] = 0
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Memory forms

aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPPS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE instructions

• ADDPS
• ADDSS
• ANDNPS
• ANDPS
• CMPSS
• COMISS
• CVTPI2PS
• CVTPS2PI
• CVTSI2SS
• CVTSS2SI
• CVTTPS2PI
• CVTTSS2SI
• DIVPS
• DIVSS
• LDMXCSR
• MASKMOVQ
• MAXPS
• MAXSS
• MINPS
• MINSS
• MOVAPS
• MOVHLPS
• MOVHPS
• MOVLHPS
• MOVLPS
• MOVMSKPS
• MOVNTPS
• MOVNTQ
• MOVSS
• MOVUPS
• MULPS
• MULSS
• ORPS
• PAVGB
• PAVGW
• PEXTRW
• PINSRW
• PMAXSW
• PMAXUB
• PMINSW

All 65 SSE instructions