Extensions
Mnemonics
CMPS, CMPSB, CMPSW, CMPSD, CMPSQ
Forms
12 (12 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of CMPS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CMPSB CMPSBA6Base instruction set
CMPSW CMPSW66 A7Base instruction set
CMPSD CMPSDA7Base instruction set
CMPSQ 64-bit mode only CMPSQREX.W A7LM
REPE CMPSB REPE_CMPSBF3 A6Base instruction set
REPNE CMPSB REPNE_CMPSBF2 A6Base instruction set
REPE CMPSW REPE_CMPSW66 F3 A7Base instruction set
REPNE CMPSW REPNE_CMPSW66 F2 A7Base instruction set
REPE CMPSD REPE_CMPSDF3 A7Base instruction set
REPNE CMPSD REPNE_CMPSDF2 A7Base instruction set
REPE CMPSQ 64-bit mode only REPE_CMPSQF3 REX.W A7LM
REPNE CMPSQ 64-bit mode only REPNE_CMPSQF2 REX.W A7LM

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
I86

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
I386

No CPUID bit: part of the base instruction set.

Every x86-64 processor in XED’s model
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.