Instruction
CMPS
Compares the element at [RSI] with the one at [RDI], setting the flags as CMP would, and steps both pointers; REPE and REPNE repeat it.
- Extensions
- Mnemonics
- CMPS, CMPSB, CMPSW, CMPSD, CMPSQ
- Forms
- 12 (12 Legacy)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
CMPSB
CMPSB | A6 | Base instruction set |
CMPSW
CMPSW | 66 A7 | Base instruction set |
CMPSD
CMPSD | A7 | Base instruction set |
CMPSQ 64-bit mode only
CMPSQ | REX.W A7 | LM |
REPE CMPSB
REPE_CMPSB | F3 A6 | Base instruction set |
REPNE CMPSB
REPNE_CMPSB | F2 A6 | Base instruction set |
REPE CMPSW
REPE_CMPSW | 66 F3 A7 | Base instruction set |
REPNE CMPSW
REPNE_CMPSW | 66 F2 A7 | Base instruction set |
REPE CMPSD
REPE_CMPSD | F3 A7 | Base instruction set |
REPNE CMPSD
REPNE_CMPSD | F2 A7 | Base instruction set |
REPE CMPSQ 64-bit mode only
REPE_CMPSQ | F3 REX.W A7 | LM |
REPNE CMPSQ 64-bit mode only
REPNE_CMPSQ | F2 REX.W A7 | LM |
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
I86 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
I386 | No CPUID bit: part of the base instruction set. | Every x86-64 processor in XED’s model |
LONGMODE | LM | Every x86-64 processor in XED’s model |
More General-purpose instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
- Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.