CMPS

CMPS compares the element at [RSI] with the one at [RDI], setting the flags as a CMP of the first with the second would, and moves both pointers to the next element. With a REPE prefix it walks two buffers until they differ, the core of memcmp; with REPNE it walks them until a pair is equal. The doubleword form shares its name with SSE2’s CMPSD, a comparison of doubles.

REPE CMPS as memcmp#

With the buffers in RSI and RDI, the length in RCX and the direction flag clear, repe cmpsb stops after the first pair of bytes that differ, or when RCX reaches 0. Afterwards:

• ZF set means every byte compared was equal.
• ZF clear means the bytes at RSI - 1 and RDI - 1 differ, and CF gives their order as unsigned numbers, as memcmp needs: JB when the byte of the first buffer is the smaller.
• RCX holds the number of bytes left uncompared.

The trap is a length of 0. The instruction then compares nothing and changes no flag, so ZF still holds whatever an earlier instruction left there; the code must test RCX first, or set ZF itself, for instance with cmp rcx, rcx.

Speed#

Intel’s optimization manual advises against REP CMPS and REP SCAS for performance and points to SIMD code instead (Section 3.7.5). Its processors from Golden Cove on report faster REPE and REPNE CMPSB and SCASB, for 1 to 128 bytes held in the first-level cache, in CPUID.(EAX=7,ECX=1):EAX[12], and the manual gives them a flat 15 cycles in that range (Section 3.8.3). The instruction table of AMD’s Zen 5 guide lists CMPSB as microcoded.

GCC 14 and Clang 23 at -O2 call memcmp for comparisons of unknown length, and inline those of a small known size without CMPS: memcmp(a, b, 16) == 0 becomes two quadword XORs and an OR in GCC, and PCMPEQB with PMOVMSKB in Clang.

A fault in the middle of a REPE or REPNE CMPS, such as a page fault on a later element, leaves RSI, RDI and RCX at the element that faulted, and the flags as they were before the instruction, so it resumes cleanly; see MOVS for the direction flag and the 67 prefix.

In the optimization guide

What the optimization guide says about CMPS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Memory

• REP MOVS and STOS: Intel’s cores made rep movsb and rep stosb fast from Ivy Bridge, and short strings fast from Ice Lake and Golden Cove, as CPUID reports.

Golden Cove and Raptor Cove

• Loads, stores and caches: Short rep movsb, rep stosb, rep cmpsb and rep scasb are fast: with the data in the L1 cache, any length up to 128 bytes takes a flat 9, 12, 15 and 15 cycles, zero included except for the compares.

Forms

Latency and throughput

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

step = -(OSIZE // 8) if df else OSIZE // 8
a = load(aSI, OSIZE)
b = load(aDI, OSIZE)
flags = sub_flags(a, b)          # [rSI] - [rDI]
aSI = low(aSI + step, ASIZE)
aDI = low(aDI + step, ASIZE)

step = -(OSIZE // 8) if df else OSIZE // 8
s = aSI
d = aDI
c = aCX
for i in range(aCX):             # no flag changes when aCX is 0
    a = load(s, OSIZE)
    b = load(d, OSIZE)
    flags = sub_flags(a, b)
    s = low(s + step, ASIZE)
    d = low(d + step, ASIZE)
    c -= 1
    if a != b:
        break                    # ZF clear: the first difference
aSI = s
aDI = d
aCX = c

step = -(OSIZE // 8) if df else OSIZE // 8
s = aSI
d = aDI
c = aCX
for i in range(aCX):
    a = load(s, OSIZE)
    b = load(d, OSIZE)
    flags = sub_flags(a, b)
    s = low(s + step, ASIZE)
    d = low(d + step, ASIZE)
    c -= 1
    if a == b:
        break                    # ZF set: the first match
aSI = s
aDI = d
aCX = c

Operands

Flags

Attributes

What else XED records about the forms. How to read.

REP forms

repeated: count in rCX

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

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