CMPSD instruction (SSE2)

CMPSD compares the low doubles of its operands under one of the eight predicates of CMPPS, picked by bits 2:0 of the immediate, and writes all ones or zero to the low quadword; the high double of the destination keeps its value. On Zen 5, the recorded cmpsd xmm8, xmm15, 0x7 found 1.0 and -2^-53 ordered, wrote all ones and left the +infinity in bits 127:64 alone. CMPSS describes the scalar compares in more detail, from the choice between a mask and COMISD’s flags to the intrinsics without a predicate of their own; this page adds what is particular to doubles.

One name, two instructions

The string instruction that compares doublewords, CMPS in its CMPSD form, has the same mnemonic. Assemblers tell them apart by the operands: none or two memory operands for the string form, an XMM register and an immediate for this one. GCC and Clang print this one as a pseudo-op that names the predicate, such as CMPLTSD.

In compiled code

In our builds at -O2 for the x86-64 baseline, branchless code over double uses the mask as CMPSS does for float:

x >= 2.0 ? 1.0 : 0.0 is CMPLESD with the operands swapped and an ANDPD with 1.0 in Clang 23. GCC 14 branches on COMISD instead, and with -march=x86-64-v2 computes not-less-or-equal and selects with BLENDVPD.
C’s fmax, which returns the other argument when one is a NaN, is a library call in GCC. Clang inlines it as MAXSD, which returns its second operand when either is a NaN, and fixes that case with cmpunordsd x, x on the first argument and a select.

_mm_cmpgt_sd again has no predicate of its own and keeps the high double of its first argument: GCC compares with CMPLTPD and merges with MOVSD, Clang uses CMPLTSD and MOVSD, or BLENDPD with x86-64-v2.

AMD’s latency spreadsheet for Zen 5 gives CMPSD two cycles on pipes FP2 and FP3. The memory form reads eight bytes at any alignment, and the legacy form keeps bits 255:128 of its register (see mixing SSE and AVX). VCMPSD is the VEX and EVEX form, with the 32 predicates of VCMPPS.

Forms

Every encoding of CMPSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CMPSD xmm, m64, imm8` CMPSD_XMM_XMMsd_MEMsd_IMMb	`F2 0F C2 /r ib`	SSE2
`CMPSD xmm, xmm, imm8` CMPSD_XMM_XMMsd_XMMsd_IMMb	`F2 0F C2 /r ib`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from double 0 of xmm1 and xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = xmm1.f64[0]
b = src2.f64[0]
if fcmp(imm8 & 7, a, b):
    xmm1.q[0] = -1
else:
    xmm1.q[0] = 0
# xmm1.q[1] keeps its value
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CMPSD xmm, xmm/m64, imm8`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cmp_sd` `__m128d _mm_cmp_sd(__m128d a, __m128d b, const int c)`	`CMPSD xmm, xmm, imm8` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

One name, two instructions#

In compiled code#