CMPSS

CMPSS compares only the low singles of its operands, under one of the eight predicates of CMPPS chosen by bits 2:0 of the immediate, and writes all ones or zero to the low doubleword of the destination. Singles 1 to 3 keep their values, so the destination is an input as well. On Zen 5, the recorded cmpss xmm12, xmm6, 0x11 found the smallest normal single less than 0.5 and wrote FFFFFFFFh, keeping the 1.0, -1.0 and 0 above it. The memory form reads four bytes at any alignment.

A mask or the flags#

COMISS and UCOMISS also compare the low singles but set EFLAGS, and compilers take them whenever a branch, SETcc or CMOVcc uses the answer. CMPSS appears when the answer selects between two singles without a branch. In our builds at -O2 for the x86-64 baseline:

• a < b ? c : d over float is a CMPSS followed by ANDPS, ANDNPS and ORPS: Clang 23 computes less-than, GCC 14 not-less-than with c and d swapped. With -march=x86-64-v2 the three logic instructions become one BLENDVPS.
• x < 1.0f ? 1.0f : 0.0f needs no select: the mask ANDed with 1.0 gives 1.0 or +0.0.
• A select that amounts to a minimum or maximum, such as a > b ? a : b, is MAXSS instead.

FFFFFFFFh read as a single is a NaN, so the mask is for the logic instructions, never for arithmetic.

Intrinsics without a predicate#

_mm_cmpgt_ss(a, b) must keep singles 1 to 3 of a, but the eight predicates have no greater-than: it is less-than with the operands swapped, which would keep those of b. Both compilers therefore compare into the other register and merge the low element back: GCC with a packed CMPLTPS and MOVSS, Clang with CMPLTSS and MOVSS, or BLENDPS for x86-64-v2.

AMD’s latency spreadsheet for Zen 5 gives CMPSS two cycles on pipes FP2 and FP3, as for the packed form. The legacy form keeps bits 255:128 of its register (see mixing SSE and AVX); VCMPSS has the 32 predicates of VCMPPS: its VEX form takes the upper singles from a separate source, its EVEX form writes a mask register. CMPSD is the double-precision form.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = xmm1.f32[0]
b = src2.f32[0]
if fcmp(imm8 & 7, a, b):
    xmm1.d[0] = -1
else:
    xmm1.d[0] = 0
# xmm1.d[1] to [3] keep their values
# imm8 & 7: 0 ==, 1 <, 2 <=, 3 unordered, 4 !=, 5 !<, 6 !<=, 7 ordered
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CMPSS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE instructions

• ADDPS
• ADDSS
• ANDNPS
• ANDPS
• CMPPS
• COMISS
• CVTPI2PS
• CVTPS2PI
• CVTSI2SS
• CVTSS2SI
• CVTTPS2PI
• CVTTSS2SI
• DIVPS
• DIVSS
• LDMXCSR
• MASKMOVQ
• MAXPS
• MAXSS
• MINPS
• MINSS
• MOVAPS
• MOVHLPS
• MOVHPS
• MOVLHPS
• MOVLPS
• MOVMSKPS
• MOVNTPS
• MOVNTQ
• MOVSS
• MOVUPS
• MULPS
• MULSS
• ORPS
• PAVGB
• PAVGW
• PEXTRW
• PINSRW
• PMAXSW
• PMAXUB
• PMINSW

All 65 SSE instructions