x86-64.net

Instruction

CMPXCHG16B

Compares RDX:RAX with 16 aligned bytes of memory: if equal, stores RCX:RBX there and sets ZF, else loads them into RDX:RAX; atomic with LOCK.

Extensions
Forms
2 (2 Legacy)
Data
Intel XED v2026.08.23

Forms

Every encoding of CMPXCHG16B that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CMPXCHG16B m128 64-bit mode only CMPXCHG16B_MEMdqREX.W 0F C7 /1CMPXCHG16B
LOCK CMPXCHG16B m128 64-bit mode only CMPXCHG16B_LOCK_MEMdqREX.W 0F C7 /1CMPXCHG16B

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
CMPXCHG16B

CMPXCHG16B
CPUID.01H:ECX[13] CMPXCHG16B

Every x86-64 processor in XED’s model

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.