COMISD instruction (SSE2)

COMISD compares the low doubles of two operands and puts the answer in EFLAGS, the way COMISS does for singles: greater clears ZF, PF and CF, less sets CF, equal sets ZF, and unordered (a NaN on either side) sets all three, with OF, SF and AF always cleared. UCOMISD is the quiet version, and COMISS’s page explains the unsigned-compare pattern the flags follow and why compilers swap the operands for “less than”. On Zen 5, in a masked case with DAZ set, comparing -0.0 against -0.0 read from memory gave “equal”, ZF set and PF and CF clear, with no new flag: zeros of either sign compare equal, raising no exception.

Ordered and unordered

GCC 14 and Clang 23 at -O2 compile a < b and a <= b over double to COMISD and SETAE or SETA with the operands swapped, as COMISS’s page shows for float, and both use UCOMISD for ==, != and the quiet macros such as isless(), since a quiet NaN needs no exception there. For == and != specifically, Clang does not reach for UCOMISD at all: it compiles both to CMPEQSD or CMPNEQSD, a mask in an XMM register narrowed to a flag with MOVQ and AND, while GCC keeps testing ZF and PF after UCOMISD as COMISS’s page describes. With -ffp-exception-behavior=strict, Clang switches < and <= to COMISD, matching GCC.

COMISD raises IE for any NaN, a quiet one included; UCOMISD only for a signaling one. AMD’s latency spreadsheet for Zen 5 gives it two macro-ops, on pipes FP2/FP3 and FP4/FP5, two per cycle, with no latency listed since it writes no register. VCOMISD is the VEX and EVEX form, and COMISS compares singles.

Forms

Every encoding of COMISD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`COMISD xmm, m64` COMISD_XMMsd_MEMsd	`66 0F 2F /r`	SSE2
`COMISD xmm, xmm` COMISD_XMMsd_XMMsd	`66 0F 2F /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low doubles of the two sources are compared, and the result sets ZF, PF and CF.

The flags come from double 0 of xmm1 and xmm2. RFLAGS: CF, PF, ZF.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.f64[0], src2.f64[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# a QNaN raises IE too

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`COMISD xmm, xmm/m64`
`xmm`	explicit	read
`xmm/m64`	explicit	read
`RFLAGS`	implicit	write

Flags

M modified, 0 cleared; blank: not affected. How to read.

OF	SF	ZF	AF	PF	CF
All forms
0	0	M	0	M	M

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to COMISD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_comieq_sd` `int _mm_comieq_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2
`_mm_comige_sd` `int _mm_comige_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2
`_mm_comigt_sd` `int _mm_comigt_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2
`_mm_comile_sd` `int _mm_comile_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2
`_mm_comilt_sd` `int _mm_comilt_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2
`_mm_comineq_sd` `int _mm_comineq_sd(__m128d __a, __m128d __b)`	`COMISD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Ordered and unordered#