COMISS

COMISS compares the low singles of two operands and puts the answer in EFLAGS, where a conditional jump, SETcc or CMOVcc can use it at once; CMPSS gives a mask in an XMM register instead. The flags follow the pattern of the x87 FCOMI: greater clears ZF, PF and CF, less sets CF, equal sets ZF, and unordered (a NaN on either side) sets all three. OF, SF and AF are cleared.

Reading the flags#

The pattern is that of an unsigned compare, so the unsigned conditions apply, but those that test CF or ZF alone also hold for a NaN:

• B and BE are true when the result is unordered. Compilers therefore swap the operands and use A or AE, which are false for a NaN: GCC 14 at -O2 compiles a < b to comiss xmm1, xmm0 (b against a) and seta, and a <= b to the same compare and SETAE. Clang 23 does the same with UCOMISS.
• E is true when the result is unordered, so a == b needs PF as well: GCC tests NP besides E, and both compilers branch on JNE and on JP.
• P alone means unordered: isnan(x) becomes UCOMISS of x with itself and SETP.

Ordered and unordered#

COMISS raises the invalid-operation exception for any NaN input, a quiet one included; UCOMISS only for a signaling NaN. In IEEE 754, and in C’s Annex F, <, <=, > and >= signal invalid on a NaN while == and != do not, and GCC 14 follows that: COMISS for the relational operators, UCOMISS for equality and for the quiet macros such as isless(). Clang 23 uses UCOMISS for all of them unless -ffp-exception-behavior=strict asks it to keep the exceptions; then it emits COMISS for < too. With the exception masked, as MXCSR masks all of them by default, the only difference is MXCSR.IE being set; unmasked, COMISS raises #XM and leaves EFLAGS unchanged.

AMD’s COMISS page never mentions quiet NaNs: its exception table names only signaling NaNs as a cause of IE, as on its UCOMISS page. Zen 5 sets IE for a quiet NaN all the same, as the recorded VCOMISS cases show; {sae} suppresses the flag.

VCOMISS is the VEX and EVEX form, and COMISD compares doubles. AVX10.2’s VCOMXSS sets the flags so that each relation is a single condition code, false for a NaN.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = comi(xmm1.f32[0], src2.f32[0])  # 0 >, 1 <, 2 =, 3 unordered
zf = x in (2, 3)
pf = x == 3
cf = x in (1, 3)
of = sf = af = 0
# a QNaN raises IE too

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to COMISS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE instructions

• ADDPS
• ADDSS
• ANDNPS
• ANDPS
• CMPPS
• CMPSS
• CVTPI2PS
• CVTPS2PI
• CVTSI2SS
• CVTSS2SI
• CVTTPS2PI
• CVTTSS2SI
• DIVPS
• DIVSS
• LDMXCSR
• MASKMOVQ
• MAXPS
• MAXSS
• MINPS
• MINSS
• MOVAPS
• MOVHLPS
• MOVHPS
• MOVLHPS
• MOVLPS
• MOVMSKPS
• MOVNTPS
• MOVNTQ
• MOVSS
• MOVUPS
• MULPS
• MULSS
• ORPS
• PAVGB
• PAVGW
• PEXTRW
• PINSRW
• PMAXSW
• PMAXUB
• PMINSW

All 65 SSE instructions