CPUID instruction (General-purpose)

CPUID is how software learns what processor it runs on and what that processor can do. Put a leaf number in EAX, and for leaves with sub-leaves a sub-leaf number in ECX, execute CPUID, and read the answer from EAX, EBX, ECX and EDX. It works at every privilege level and in every mode; the ID flag, bit 21 of EFLAGS, says whether a processor has it at all, which every x86-64 processor does.

The main leaves

00H returns the highest basic leaf in EAX and the vendor string, such as “GenuineIntel”, in EBX, EDX and ECX.
01H returns the family, model and stepping in EAX and the older feature bits in ECX and EDX, among them SSE2, SSE4.2, AVX and OSXSAVE.
07H holds the structured extended feature bits, spread over sub-leaves: sub-leaf 0 has AVX2, BMI1, BMI2 and AVX-512, sub-leaf 1 newer ones such as AVX-VNNI and APX.
0DH describes the state components that XSAVE manages: which ones the processor supports and the sizes and offsets of their areas.
80000000H returns the highest extended leaf, 80000001H the bits that came with the 64-bit extensions (64-bit mode itself, SYSCALL, LAHF and SAHF in 64-bit mode, LZCNT, PREFETCHW), and 80000002H to 80000004H the 48-byte brand string.
40000000H to 4FFFFFFFH return no processor information; they are left for software to emulate, which hypervisors do.

A leaf above the highest supported one returns the data of the highest basic leaf instead of zeros, so software reads leaf 00H or 80000000H first.

Reading the bits

The CPUID rows of this reference use the manuals’ notation: CPUID.(EAX=07H,ECX=0):EBX[5] is bit 5 of EBX from leaf 07H, sub-leaf 0, the AVX2 bit. Some features also need the operating system: AVX registers are usable only when leaf 01H reports OSXSAVE and XCR0, read with XGETBV, has the AVX state enabled. The x86-64 levels are defined as sets of these bits, and Check shows how to query them.

Other uses

CPUID is a serializing instruction: everything before it completes before anything after it starts. Benchmarks long used it to fence timed code; on processors with SERIALIZE, Intel recommends that instruction instead. Under Intel VT-x, CPUID always causes a VM exit, so the hypervisor decides what a guest sees, which is why a virtual machine can report a lower x86-64 level than its host.

Forms

Every encoding of CPUID that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CPUID` CPUID	`0F A2`	Base instruction set

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.

ISA set	CPUID	Processors in XED
`I486REAL` General-purpose	No CPUID bit: part of the base instruction set.	Every x86-64 processor in XED’s model

More General-purpose instructions

All 109 General-purpose instructions

The main leaves#

Reading the bits#

Other uses#