x86-64.net

Instruction

CQO

Sign-extends RAX into RDX:RAX, filling RDX with the sign bit of RAX, typically before a 64-bit IDIV (AT&T cqto); 64-bit mode only.

Extensions
Forms
1 (1 Legacy)
Data
Intel XED v2026.08.23

CQO fills RDX with copies of the sign bit of RAX, so that RDX:RAX holds the value of RAX as a signed 128-bit number. That is the dividend IDIV takes, and the two come in pairs: GCC 14 at -O2 compiles a / b on two longs to mov rax, rdi, cqo and idiv rsi, and a % b the same way, with the remainder taken from RDX. CQO changes no flag.

The family

Opcode 99 extends rAX into rDX at each operand size, and 98 extends the lower half of rAX into the whole of it:

OpcodeExtendsInstructionAT&T
REX.W 99RAX into RDX:RAXCQOcqto
99EAX into EDX:EAXCDQcltd
66 99AX into DX:AXCWDcwtd
REX.W 98EAX into RAXCDQEcltq
98AX into EAXCWDEcwtl
66 98AL into AXCBWcbtw

Both compilers divide ints, and shorts too, with CDQ and a 32-bit IDIV.

Signed and unsigned

The unsigned DIV needs zeros in the upper half instead, which compilers write with xor edx, edx. Mixing the two up is a classic bug: CQO before DIV turns a dividend with its top bit set into one whose upper half is all ones, and DIV then raises #DE, as the quotient cannot fit. Intel’s optimization manual notes that CDQ and CWD cost as many micro-ops as the MOV and shift they replace, being only shorter, and suggests the XOR when the dividend is known not to be negative (Section 3.5.1.1).

Clang 23 uses the XOR on a path of its own. For a / b on longs it first checks whether both operands fit in 32 bits, with or rcx, rsi on a copy of a and shr rcx, 32, and if they do, it divides with xor edx, edx and a 32-bit DIV; only otherwise does it run CQO and the 64-bit IDIV.

Other ways to the sign

CQO writes only RDX, and only from RAX. A sign mask in any other register is a SAR by 63, which both compilers emit for x >> 63 on a long. To widen a long to __int128, GCC uses CQO and Clang a MOV and a SAR.

In the optimization guide

What the optimization guide says about CQO, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Zen 4

  • Integer execution: xor edx, edx before DIV, or CDQ or CQO before IDIV, with the same operand size and a divisor in a register other than rDX, saves a macro-op: the pair is dispatched as one fewer.

Forms

Every encoding of CQO that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CQO 64-bit mode only CQOREX.W 99LM

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
ModelCQO
Sandy Bridge1 / 0.5p05
Haswell, Broadwell, Skylake, Skylake-SP, Ice Lake, Alder Lake, Sapphire Rapids1 / 0.5p06
Lunar Lake1 / 0.33p024
Bonnell4 / 2p01
Silvermont1 / 0.5IEC0 IEC1
Piledriver1 / 1EX0 EX1
Zen, Zen 2, Zen 3, Zen 41 / 0.25ALU0 ALU1 ALU2 ALU3
Jaguar1 / 0.5ALU0 ALU1

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

rdx = -1 if msb(rax) else 0

Run on AMD Zen 5 (EPYC 9645): 8 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
CQO 64-bit mode only
RDXimplicitwrite
RAXimplicitread

Flags

None: XED records no flag that the forms test or change.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
LONGMODE

LM
CPUID.80000001H:EDX[29] LM

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More General-purpose instructions

All 109 General-purpose instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-257 (CWD/CDQ/CQO)
  5. AMD64 Architecture Programmer's Manual, Volume 3: General-Purpose and System Instructions (24594, rev. 3.39, October 2026)
  6. Intel 64 and IA-32 Architectures Optimization Reference Manual, Volume 1 (248966-051, October 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The timings come from LLVM's scheduling models, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.