x86-64.net

Instruction

CRC32

Accumulates a CRC-32C checksum (Castagnoli polynomial) over a 1-, 2-, 4- or 8-byte operand.

Extensions
Forms
8 (4 Legacy, 4 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of CRC32 that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CRC32 r32/64, m8 CRC32_GPRyy_MEMbF2 0F 38 F0 /rSSE4.2
CRC32 r32/64, r8 CRC32_GPRyy_GPR8bF2 0F 38 F0 /rSSE4.2
CRC32 r32/64, m16/32/64 CRC32_GPRyy_MEMvF2 0F 38 F1 /rSSE4.2
CRC32 r32/64, r16/32/64 CRC32_GPRyy_GPRvF2 0F 38 F1 /rSSE4.2
CRC32 r32/64, r8 CRC32_GPRy_GPR8i8_APXEVEX.LLZ.NP.MAP4.SCALABLE F0 /rAPX_F
CRC32 r32/64, m8 CRC32_GPRy_MEMi8_APXEVEX.LLZ.NP.MAP4.SCALABLE F0 /rAPX_F
CRC32 r32/64, r16/32/64 CRC32_GPRy_GPRv_APXEVEX.LLZ.NP.MAP4.SCALABLE F1 /rAPX_F
CRC32 r32/64, m16/32/64 CRC32_GPRy_MEMv_APXEVEX.LLZ.NP.MAP4.SCALABLE F1 /rAPX_F

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CRC32, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
__crc32b unsigned int __crc32b(unsigned int __C, unsigned char __D)

CRC32 r32/64, r8 Legacy -mcrc32

__crc32d unsigned int __crc32d(unsigned int __C, unsigned int __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

__crc32q unsigned long long __crc32q(unsigned long long __C, unsigned long long __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

__crc32w unsigned int __crc32w(unsigned int __C, unsigned short __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

_mm_crc32_u16 unsigned int _mm_crc32_u16(unsigned int __C, unsigned short __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

_mm_crc32_u32 unsigned int _mm_crc32_u32(unsigned int __C, unsigned int __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

_mm_crc32_u64 unsigned long long _mm_crc32_u64(unsigned long long __C, unsigned long long __D)

CRC32 r32/64, r16/32/64 Legacy -mcrc32

_mm_crc32_u8 unsigned int _mm_crc32_u8(unsigned int __C, unsigned char __D)

CRC32 r32/64, r8 Legacy -mcrc32

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
SSE42

SSE4.2
CPUID.01H:ECX[20] SSE4.2

Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Silvermont, Goldmont, Goldmont Plus, Tremont, Snow Ridge, Lakefield, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, K10 (Family 10h), Bulldozer, Piledriver, Zen, Zen+, Zen 2

Note: XED's AMD_K10 inherits everything from its Westmere chip, including SSSE3, SSE4.1, SSE4.2, AES-NI and PCLMULQDQ; GCC's -march=amdfam10 has none of them.

APX_F

APX_F
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.