CTESTscc

CTESTscc is a TEST that runs only if a condition on the current flags holds. It lets a compiler join a == 1 && (b & c) without a branch: one flag-setting compare, then a test that either updates the flags from its operands or, when the first half has already failed, loads them with a value that gives the answer. It is CCMPscc with TEST in place of CMP, and it writes no register.

The source condition uses the usual condition codes, with two changes: codes 1010b and 1011b, parity elsewhere, mean always true and always false, so PF cannot be tested. CTESTT is then a plain TEST, and CTESTF just writes the flags.

• If the condition holds, the flags come from src1 & src2 as for TEST: OF and CF cleared, SF, ZF and PF from the result, AF undefined.
• If not, OF, SF, ZF and CF take the four-bit default flags value (dfv) in the instruction. PF copies its CF bit and AF is cleared.

The forms match TEST’s: a register or memory operand of 8, 16, 32 or 64 bits with a register or an immediate, which is at most 32 bits and sign-extended at 64. A memory operand is read whatever the condition says, so it can fault; only CFCMOVcc suppresses faults this way.

In our builds#

Clang 23 at -O2 with -mapxf compiled a == 1 && (b & c) to cmp edi, 1, cteste {dfv=zf} edx, esi and setzune al. If a is 1 the test runs; otherwise dfv sets ZF, which SETNE then reads as false. a > 3 || (b & c) became cmp edi, 4 and ctestl {dfv=}, with every default flag clear, so that SETNE reads true when the first half has decided it. With a load, a == 1 && (*m & 8), Clang kept a branch, which fits the rule above. GCC 14 accepts -mapxf but used no CTESTscc in any of these.

The condition instructions need APX_NCI_NDD_NF as well as APX_F, as the APX page explains.

Forms

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = src1 & sext(src2)            # memory is read, and can fault, even
                                 # when the condition is false
if cond(CC):
    of = cf = 0                  # as TEST src1, src2
    sf = msb(r)
    zf = r == 0
    pf = parity(r)
    af = UNDEFINED
else:
    of = dfv >> 3 & 1            # the flags of {dfv}
    sf = dfv >> 2 & 1
    zf = dfv >> 1 & 1
    cf = dfv & 1
    pf = dfv & 1                 # PF as CF
    af = 0

Operands

Flags

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

APX-EVEX-CCMP

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More APX instructions

• AADD
• AAND
• ADC
• ADCX
• ADD
• ADOX
• AND
• ANDN
• AOR
• AXOR
• BEXTR
• BLSI
• BLSMSK
• BLSR
• BZHI
• CCMPscc
• CFCMOVcc
• CMOVcc
• CMPccXADD
• CRC32
• DEC
• DIV
• ENQCMD
• ENQCMDS
• IDIV
• IMUL
• INC
• INVEPT
• INVPCID
• INVVPID
• JMPABS
• KMOVB
• KMOVD
• KMOVQ
• KMOVW
• LDTILECFG
• LZCNT
• MOVBE
• MOVDIR64B
• MOVDIRI

All 88 APX instructions