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Instruction

CTESTscc

APX conditional test: if the flags meet a condition, tests two operands with AND, otherwise sets OF, SF, ZF and CF to a value in the instruction.

Extensions
Mnemonics
CTESTO, CTESTNO, CTESTB, CTESTC, CTESTNAE, CTESTNB, CTESTNC, CTESTAE, CTESTZ, CTESTE, CTESTNZ, CTESTNE, CTESTBE, CTESTNA, CTESTNBE, CTESTA, CTESTS, CTESTNS, CTESTT, CTESTF, CTESTL, CTESTNGE, CTESTNL, CTESTGE, CTESTLE, CTESTNG, CTESTNLE, CTESTG
Forms
8 (8 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of CTESTscc that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CTESTscc {dfv} r8, r8 CTESTscc_GPR8i8_GPR8i8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 84 /r SC=sccAPX_F + APX_NCI_NDD_NF
CTESTscc {dfv} m8, r8 CTESTscc_MEMi8_GPR8i8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG 84 /r SC=sccAPX_F + APX_NCI_NDD_NF
CTESTscc {dfv} r16/32/64, r16/32/64 CTESTscc_GPRv_GPRv_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 85 /r SC=sccAPX_F + APX_NCI_NDD_NF
CTESTscc {dfv} m16/32/64, r16/32/64 CTESTscc_MEMv_GPRv_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE 85 /r SC=sccAPX_F + APX_NCI_NDD_NF
CTESTscc {dfv} r8, imm8 CTESTscc_GPR8i8_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /0 ib SC=scc
EVEX.LLZ.NP.MAP4.WIG F6 /1 ib SC=scc		APX_F + APX_NCI_NDD_NF
CTESTscc {dfv} m8, imm8 CTESTscc_MEMi8_IMM8_DFV_APX_N3EVEX.LLZ.NP.MAP4.WIG F6 /0 ib SC=scc
EVEX.LLZ.NP.MAP4.WIG F6 /1 ib SC=scc		APX_F + APX_NCI_NDD_NF
CTESTscc {dfv} r16/32/64, imm16/32 CTESTscc_GPRv_IMMz_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /0 iw/id SC=scc
EVEX.LLZ.NP.MAP4.SCALABLE F7 /1 iw/id SC=scc		APX_F + APX_NCI_NDD_NF
CTESTscc {dfv} m16/32/64, imm16/32 CTESTscc_MEMv_IMMz_DFV_APX_N3EVEX.LLZ.NP.MAP4.SCALABLE F7 /0 iw/id SC=scc
EVEX.LLZ.NP.MAP4.SCALABLE F7 /1 iw/id SC=scc		APX_F + APX_NCI_NDD_NF

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
APX_F_N3

APX_F + APX_NCI_NDD_NF
CPUID.(EAX=07H,ECX=1):EDX[21] APX_F
CPUID.(EAX=29H,ECX=0):EBX[0] APX_NCI_NDD_NF

Nova Lake, Diamond Rapids

More APX instructions

All 88 APX instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Intel Advanced Performance Extensions (Intel APX) Architecture Specification, revision 7.0 (July 2025)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.