CVTDQ2PD instruction (SSE2)

CVTDQ2PD converts the two low signed doublewords of its source to two doubles. A double’s 53-bit significand holds every 32-bit integer, so the conversion is always exact: no rounding, no flag, and MXCSR plays no part. On Zen 5, 7FFFFFC0h and -2 became 2,147,483,584.0 and -2.0 with MXCSR set to round toward zero, and MXCSR came back unchanged. The memory form reads only eight bytes, with no alignment requirement.

Because the result is twice as wide as the input, one instruction converts only half of an XMM register’s worth of integers. CVTDQ2PS takes all four, but to singles, which round above 2^24; CVTSI2SD converts one integer from a general-purpose register.

In compiled code

Both compilers vectorize d[i] = s[i] from an int array to a double array at -O2 with SSE2, two ways:

GCC 14 loads 16 bytes, converts the low pair, moves the high pair down with pshufd xmm0, xmm0, 0EEh and converts again;
Clang 23 uses the memory form, four CVTDQ2PD per iteration, each reading the next eight bytes.

For unsigned elements the signed conversion is wrong from 2^31 up. GCC converts as signed and adds 2^32 to the elements that came out negative (CMPLTPD, ANDPD and ADDPD). Clang skips CVTDQ2PD: it places each integer in the low bits of the double 2^52, whose significand then holds it exactly, and subtracts 2^52.

A loop that sums s[i] * 0.5 into one double stays scalar, a CVTSI2SD per element: vectorizing would reorder the additions, which C does not allow without -ffast-math or the like.

Wider forms

VCVTDQ2PD, the VEX form, converts four doublewords from an XMM register into a YMM register, which is how the same loop compiles with -mavx2; the EVEX form converts eight into a ZMM register, with masking and broadcast. AMD’s Zen 5 guide lists the 128-bit form as one macro-op with a latency of three cycles and the 256-bit form from a register as two. CVTPD2DQ and CVTTPD2DQ convert back, and those may round.

Forms

Every encoding of CVTDQ2PD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTDQ2PD xmm, m64` CVTDQ2PD_XMMpd_MEMq	`F3 0F E6 /r`	SSE2
`CVTDQ2PD xmm, xmm` CVTDQ2PD_XMMpd_XMMq	`F3 0F E6 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each doubleword becomes a double, converted, in the same order.

Result doubles 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f64[i] = to_f64(src2.sd[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTDQ2PD xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_5

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTDQ2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi32_pd` `__m128d _mm_cvtepi32_pd(__m128i __a)`	`CVTDQ2PD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#

Wider forms#