CVTDQ2PS instruction (SSE2)

CVTDQ2PS converts four signed doublewords to singles. A single has a 24-bit significand, so every integer up to 2^24 (16,777,216) in magnitude converts exactly, and larger ones may not: 16,777,217 becomes 16,777,216 under the default rounding. Such a result is rounded as MXCSR.RC says and sets PE, the precision flag, which is masked by default; no other exception is possible, since every 32-bit integer is within the range of a single. Converting to doubles, CVTDQ2PD is always exact, but it takes only two elements. The intrinsic is _mm_cvtepi32_ps.

In compiled code

GCC 14 and Clang 23 at -O2 vectorize (float)a[i] over an int array to CVTDQ2PS, four elements per instruction. Smaller integers are widened first: for pixels, a[i] * (1.0f / 255) over uint8_t becomes PUNPCKLBW and PUNPCKLWD against zero, CVTDQ2PS and MULPS, in both compilers.

Unsigned integers

There is no unsigned form before AVX-512, and a uint32_t of 2^31 or more read as signed is negative. The compilers work around it in different ways for the SSE2 baseline:

GCC splits each element into its high and low 16 bits, converts both halves with CVTDQ2PS, multiplies the high one by 65,536 and adds.
Clang does not convert at all: it ORs each half into the significand of a float constant whose exponent makes that half’s value exact, and removes the constants with a subtraction and an addition.

With -mavx512f -mavx512vl, both use VCVTUDQ2PS instead.

Intel’s optimization manual lists CVTDQ2PS and CVTPS2DQ, the conversion back, among the operations of the units that add and compare floats in Golden Cove (Table 2-4). VCVTDQ2PS is the VEX and EVEX form; the EVEX form can take a rounding mode in the instruction for a register source, masks elements and broadcasts a doubleword from memory. The legacy form with a memory operand needs it aligned to 16 bytes.

Forms

Every encoding of CVTDQ2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTDQ2PS xmm, m128` CVTDQ2PS_XMMps_MEMdq	`NP 0F 5B /r`	SSE2
`CVTDQ2PS xmm, xmm` CVTDQ2PS_XMMps_XMMdq	`NP 0F 5B /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.

Result doubleword i comes from doubleword i of xmm2. Result doublewords 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.f32[i] = to_f32(src2.sd[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTDQ2PS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTDQ2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtepi32_ps` `__m128 _mm_cvtepi32_ps(__m128i __a)`	`CVTDQ2PS xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

In compiled code#

Unsigned integers#