CVTPD2DQ instruction (SSE2)

CVTPD2DQ converts the two doubles of an XMM register, or of 16 aligned bytes of memory, to signed doublewords, rounding as MXCSR.RC says, and writes them to the low 64 bits of the destination, zeroing bits 127:64; bits 128 and up keep their old contents, as in every legacy SSE instruction. It is the rounding twin of CVTTPD2DQ, whose page covers the halved result and how compilers join two of them, and the packed form of CVTSD2SI; CVTPS2DQ explains rounding to nearest with ties to even. VCVTPD2DQ is the VEX and EVEX form.

The edge of the range

A double holds values just below 2^31 that a single cannot, and rounding decides what happens to them. Zen 5’s recorded register case, rounding to nearest, turned 2,147,483,647.9999998 into 80000000H, the integer indefinite, since it rounds up to 2^31, which does not fit; CVTTPD2DQ truncates the same value to 7FFFFFFFH. -2,147,483,649 gave 80000000H as well, and IE was set. In the memory case, rounding toward zero with DAZ, a negative denormal was read as zero and gave 0 exactly, while the smallest normal double, 2^-1022, also became 0 but set PE.

In compiled code

C’s cast truncates, so a plain (int)x is never CVTPD2DQ. In our builds at -O2 for the default target, it appears for _mm_cvtpd_epi32 and, in Clang 23, for a loop of out[i] = (int)rint(in[i]): MOVUPS loads two doubles, CVTPD2DQ converts them and MOVLPS stores the two doublewords, since rint rounds as MXCSR says. GCC 14 keeps that loop scalar, rounding with an add and subtract of 2^52 and converting with CVTTSD2SI, and with -march=x86-64-v2 with ROUNDSD first. lrint returns a long, so with -fno-math-errno both compilers convert each element with the 64-bit CVTSD2SI instead.

Forms

Every encoding of CVTPD2DQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPD2DQ xmm, m128` CVTPD2DQ_XMMdq_MEMpd	`F2 0F E6 /r`	SSE2
`CVTPD2DQ xmm, xmm` CVTPD2DQ_XMMdq_XMMpd	`F2 0F E6 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each double becomes a doubleword, in the same order, at the low end of the result; the rest of the register is zeroed.

Result doublewords 3 to 0: 0, 0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.d[i] = cvt_int(src2.f64[i], 32)
for i in range(2, 4):
    xmm1.d[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPD2DQ xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTPD2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtpd_epi32` `__m128i _mm_cvtpd_epi32(__m128d __a)`	`CVTPD2DQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

The edge of the range#

In compiled code#