CVTPD2PS instruction (SSE2)

CVTPD2PS converts the two doubles of an XMM register or of 16 bytes of memory to two singles, rounded as MXCSR.RC says, in the low 64 bits of the destination, and zeroes bits 127:64. It is the packed form of CVTSD2SS, whose page describes what narrowing does to each value: rounding, overflow to infinity, denormals, and NaNs losing the low bits of their payload.

Half a register out

Narrowing halves the width, so the result fills half of what the source did. The legacy SSE form leaves bits 255:128 of the register as they were, as the cases recorded on Zen 5 show; VEX and EVEX forms zero everything above their result. VCVTPD2PS reads a ymm register into an xmm one, and a zmm into a ymm. Because a memory source of 16 and 32 bytes both give an xmm destination, AT&T syntax needs the size in the mnemonic: the GNU assembler rejects vcvtpd2ps (%rax), %xmm0 and takes vcvtpd2psx or vcvtpd2psy.

For a loop that narrows an array of 1,024 doubles, GCC 14 and Clang 23 at -O2 differ in how they put the halves together:

For the baseline, both convert two vectors and join their low halves with MOVLHPS (GCC) or UNPCKLPD (Clang) before a 16-byte store.
With -march=x86-64-v3, GCC joins two ymm-to-xmm conversions with VINSERTF128 for a 32-byte store, and with x86-64-v4 two zmm-to-ymm ones with VINSERTF32X8; Clang stores each 16-byte result as it is.

Unmasked exceptions on Zen 5

Each element is converted on its own, and MXCSR collects the flags of both. With invalid operation unmasked, a signaling NaN in one element raised #XM and left the destination unchanged. With every exception unmasked and the other element -1.7976931348623157e308, the most negative finite double, only IE was set: that element would overflow, but an invalid operand found before the arithmetic takes precedence, and the overflow was not reported.

AMD’s Zen 5 guide lists CVTPD2PS as one macro-op with a latency of three cycles, and the ymm form of VCVTPD2PS as two with a latency of six. CVTPS2PD widens the other way, exactly.

Forms

Every encoding of CVTPD2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPD2PS xmm, m128` CVTPD2PS_XMMps_MEMpd	`66 0F 5A /r`	SSE2
`CVTPD2PS xmm, xmm` CVTPD2PS_XMMps_XMMpd	`66 0F 5A /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each double becomes a single, in the same order, at the low end of the result; the rest of the register is zeroed.

Result singles 3 to 0: 0, 0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f32[i] = to_f32(src2.f64[i])
for i in range(2, 4):
    xmm1.d[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPD2PS xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTPD2PS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtpd_ps` `__m128 _mm_cvtpd_ps(__m128d __a)`	`CVTPD2PS xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Half a register out#

Unmasked exceptions on Zen 5#