CVTPI2PS instruction (SSE)

Forms

Every encoding of CVTPI2PS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPI2PS xmm, m64` CVTPI2PS_XMMq_MEMq	`NP 0F 2A /r`	SSE
`CVTPI2PS xmm, mm` CVTPI2PS_XMMq_MMXq	`NP 0F 2A /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Only the low two singles are computed, each from the elements in the same place; the other singles come from xmm1.

Result singles 1 and 0 are computed from doublewords 1 and 0 of mm2; singles 3 and 2 are those of xmm1. Result singles 3 to 0: a3, a2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f32[i] = to_f32(src2.sd[i])
# xmm1.d[2] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPI2PS xmm, mm/m64`
`xmm`	explicit	read, write
`mm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: mmx-fp

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions