CVTPS2DQ instruction (SSE2)

CVTPS2DQ converts four singles to signed doublewords, rounding as MXCSR.RC says: to nearest, ties to even, unless the program changed it. So 2.5 becomes 2, 3.5 becomes 4 and -0.7 becomes -1. That is not what a C cast does: (int)x truncates, and compilers use CVTTPS2DQ, with the extra T, for it. CVTPS2DQ is the conversion for _mm_cvtps_epi32, and for rounding to the nearest integer when the result is wanted as an integer.

Out of range

A NaN, an infinity, or a value that rounds outside -2^31 to 2^31 - 1 gives the integer indefinite, 80000000h, the most negative doubleword, and sets IE in MXCSR, or raises #XM if IE is unmasked. The largest single below 2^31 is 2,147,483,520; 2^31 itself already becomes 80000000h, a large positive input giving a negative result. A result that needed rounding sets PE. The cases recorded on Zen 5 show the indefinite value for NaNs and infinities of both signs.

In compiled code

With -fno-math-errno, Clang 23 at -O2 vectorizes (int)rintf(a[i]) to CVTPS2DQ with the array as its memory operand, since rounding by the current mode and then converting an integral value is the same as one conversion by the current mode. GCC 14 converts such a loop one element at a time. Neither vectorizes lrintf, whose result is a long: both use the 64-bit form of CVTSS2SI per element.

Intel’s optimization manual lists CVTPS2DQ, with CVTDQ2PS, among the operations of the units that add and compare floats in Golden Cove (Table 2-4).

Other forms

VCVTPS2DQ is the VEX and EVEX form; the EVEX form can take its rounding mode from the instruction rather than from MXCSR for a register source, and can mask and broadcast. VCVTPS2UDQ gives unsigned doublewords and VCVTPS2QQ quadwords. The legacy form with a memory operand needs it aligned to 16 bytes; CVTPS2PI converts two singles to an MMX register.

Forms

Every encoding of CVTPS2DQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPS2DQ xmm, m128` CVTPS2DQ_XMMdq_MEMps	`66 0F 5B /r`	SSE2
`CVTPS2DQ xmm, xmm` CVTPS2DQ_XMMdq_XMMps	`66 0F 5B /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = cvt_int(src2.f32[i], 32)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPS2DQ xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTPS2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtps_epi32` `__m128i _mm_cvtps_epi32(__m128 __a)`	`CVTPS2DQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Out of range#

In compiled code#

Other forms#