CVTPS2PD instruction (SSE2)

CVTPS2PD converts the two low singles of an XMM register, or eight bytes of memory, to two doubles. Like CVTSS2SD, it is exact: it cannot round, overflow or underflow, so it raises only invalid for a signaling NaN (which becomes a quiet one) and denormal for a denormal input, which becomes a normal double unless MXCSR.DAZ makes it zero. The recorded cases show the edges: the smallest normal single gives 2^-126 and the largest gives the same value as a double.

Half a register in, a whole one out

A double takes twice the space of a single, so each conversion uses only half of its source. The legacy form reads 64 bits; its memory operand needs no 16-byte alignment, unlike most legacy SSE operands of packed data. VCVTPS2PD widens four singles from an XMM register or 16 bytes of memory to a YMM register, and its EVEX form eight from a YMM register to a ZMM one, so the upper half of the result comes from the lower half of the source, across the 128-bit lanes. Intel’s optimization guide counts the 256-bit form with a memory operand among the up-conversions that the Crestmont microarchitecture splits into two dependent micro-ops (Section 4.1.9.3).

Converting a float array to doubles therefore takes two conversions per vector of input. The compilers arrange that in different ways at -O2:

Clang 23 converts straight from memory, eight bytes at a time with SSE and sixteen with AVX2, so every load feeds one conversion.
GCC 14 loads a whole vector, converts its low half, moves the high half down with MOVHLPS or VEXTRACTF128, and converts that. It vectorized the loop for a constant count of 1024, but kept a scalar loop of CVTSS2SD when the count was a parameter.

The intrinsic is _mm_cvtps_pd. CVTPD2PS narrows two doubles back to singles, rounding as MXCSR says and clearing the upper half of the destination; CVTDQ2PD widens two 32-bit integers to doubles the same way, and VCVTPH2PS half-precision values to singles.

Forms

Every encoding of CVTPS2PD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPS2PD xmm, m64` CVTPS2PD_XMMpd_MEMq	`NP 0F 5A /r`	SSE2
`CVTPS2PD xmm, xmm` CVTPS2PD_XMMpd_XMMq	`NP 0F 5A /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each single becomes a double, converted, in the same order.

Result doubles 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.f64[i] = to_f64(src2.f32[i])
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPS2PD xmm, xmm/m64`
`xmm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTPS2PD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtps_pd` `__m128d _mm_cvtps_pd(__m128 __a)`	`CVTPS2PD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Half a register in, a whole one out#