CVTPS2PI instruction (SSE)

Forms

Every encoding of CVTPS2PI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTPS2PI mm, m64` CVTPS2PI_MMXq_MEMq	`NP 0F 2D /r`	SSE
`CVTPS2PI mm, xmm` CVTPS2PI_MMXq_XMMq	`NP 0F 2D /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise on the low two singles: each element of mm1 comes from the single in the same place in xmm2; the rest of xmm2 is not read.

Result element i comes from single i of xmm2, for the low two only. Result elements 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    mm1.d[i] = cvt_int(src2.f32[i], 32)
# x87: TOP = 0, all tags valid, bits 79:64 of mm1's register all ones

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTPS2PI mm, xmm/m64`
`mm`	explicit	write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: mmx-fp

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR; may abort a TSX transaction

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions