x86-64.net

Instruction

CVTSD2SI

Converts the low double to a signed 32- or 64-bit integer in a general-purpose register, rounding as MXCSR says.

Extensions
Forms
4 (4 Legacy)
Data
Intel XED v2026.08.23

CVTSD2SI converts the low double of an XMM register or of eight bytes of memory to a signed integer in a 32-bit or 64-bit general-purpose register, rounding as MXCSR.RC says, to the nearest even integer by default. It is the double-precision counterpart of CVTSS2SI, and CVTTSD2SI is its truncating sibling, the one C’s casts use.

Every int32 fits

A double holds every 32-bit integer exactly, so the 32-bit form can reach its full range: -2147483648.0 converts to 80000000h without setting IE, and so does any value that rounds to it. In the cases recorded on Zen 5, -2^31 in the 64-bit form gave FFFFFFFF80000000h with MXCSR unchanged, while negative infinity in the 32-bit form gave the integer indefinite, 80000000h, set IE, and cleared bits 63:32 of the register. The same bits for two different inputs mean that only IE tells a real -2^31 from an invalid conversion.

With round toward zero set in MXCSR, 2.5 converted to 2 and set PE, the inexact flag.

rint, lrint and lround

What reaches CVTSD2SI from C, with GCC 14 and Clang 23 at -O2:

  • lrint(x) and llrint(x) become cvtsd2si rax, xmm0 once -fno-math-errno allows it, and calls otherwise.
  • (int)rint(x) becomes cvtsd2si eax, xmm0 in Clang, even without that option, since rint never sets errno. GCC first rounds the double in an XMM register, by adding and subtracting 2^52 or with ROUNDSD under SSE4.1, and then converts with CVTTSD2SI, which gives the same result.
  • lround(x) rounds halfway cases away from zero, which no MXCSR mode does, and stays a library call.

The EVEX form VCVTSD2SI can carry a rounding mode of its own instead of MXCSR’s, and VCVTSD2USI converts to an unsigned integer.

AMD’s Zen 5 guide lists CVTSD2SI as two macro-ops, and gives its EVEX form a latency of four cycles.

Forms

Every encoding of CVTSD2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
CVTSD2SI r32, m64 CVTSD2SI_GPR32d_MEMsdF2 0F 2D /rSSE2
CVTSD2SI r32, xmm CVTSD2SI_GPR32d_XMMsdF2 0F 2D /rSSE2
CVTSD2SI r64, m64 CVTSD2SI_GPR64q_MEMsdF2 REX.W 0F 2D /rSSE2
CVTSD2SI r64, xmm CVTSD2SI_GPR64q_XMMsdF2 REX.W 0F 2D /rSSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low double of xmm2 is converted, and the integer goes to r32.
CVTSD2SI: the low element to r32r32 receives the conversion of double 0 of xmm2: r0.01xmm2ar0r32

r32 receives the conversion of double 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f64[0]
dest.write(cvt_int(a, dest.bits))  # r32: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
CVTSD2SI r32, xmm/m64 CVTSD2SI r64, xmm/m64
r32/64explicitwrite
xmm/m64explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms
SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms
follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSD2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtsd_si32 int _mm_cvtsd_si32(__m128d __a)

CVTSD2SI r32, xmm Legacy -msse2

_mm_cvtsd_si64 long long _mm_cvtsd_si64(__m128d __a)

CVTSD2SI r64, xmm Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
SSE2

SSE2
CPUID.01H:EDX[26] SSE2

Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2A, page 3-232 (CVTSD2SI)
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  6. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.