CVTSD2SS instruction (SSE2)

CVTSD2SS converts the low double of an XMM register or of eight bytes of memory to a single in the low element of an XMM register. It is the reverse of CVTSS2SD, and unlike that one it can lose information: a double carries 53 significant bits and an exponent range far beyond a single’s, so the result is rounded as MXCSR.RC says and may overflow or underflow.

What the narrowing does

An inexact result sets PE. In a case of the VEX form, VCVTSD2SS, recorded on Zen 5, -(2^31 + 1) converted under round toward zero to -2^31, with PE set.
A double above the largest single becomes infinity when rounding to nearest, with OE and PE set; rounding toward zero gives the largest finite single instead.
A result too small for a normal single becomes a denormal, or zero with FTZ set and underflow masked; with DAZ set, a denormal double counts as zero.
A NaN keeps its sign and the top 22 bits of its payload, and a signaling NaN is made quiet and sets IE. Payload bits lower down are lost: on Zen 5, VCVTSD2SS and CVTPD2PS turned the signaling NaN 7FF0000000012345h, whose payload lies entirely in its low bits, into the plain quiet NaN 7FC00000h.

In compiled code

C’s conversion from double to float is CVTSD2SS in GCC 14 and Clang 23 at -O2, and so is returning a double from a function declared to return float. Not every mix of the two types needs it: (float)((double)a * b) with float operands compiles to a single MULSS in both, since the product of two singles is exact as a double and rounding it once to single gives MULSS’s answer. Vectorized loops narrow doubles with CVTPD2PS.

The legacy form keeps bits 127:32 of its destination, so it waits for the register’s last writer, as described for CVTSS2SD; the compilers answer it the same way here, GCC with a PXOR before converting from memory and Clang by loading the double with MOVSD first. AMD’s Zen 5 guide lists CVTSD2SS among the instructions that skip that wait when the upper bits are known to be zero (Section 2.11.5), and its instruction table gives one macro-op with a latency of three cycles. VCVTSD2SS takes the upper bits from a second source; its EVEX form adds a mask and a rounding mode of its own.

Forms

Every encoding of CVTSD2SS that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTSD2SS xmm, m64` CVTSD2SS_XMMss_MEMsd	`F2 0F 5A /r`	SSE2
`CVTSD2SS xmm, xmm` CVTSD2SS_XMMss_XMMsd	`F2 0F 5A /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low single is computed; the other singles come from xmm1.

Result single 0 is computed from double 0 of xmm2; singles 3 to 1 are those of xmm1. Result singles 3 to 0: a3, a2, a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = to_f32(src2.f64[0])
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTSD2SS xmm, xmm/m64`
`xmm`	explicit	read, write
`xmm/m64`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSD2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtsd_ss` `__m128 _mm_cvtsd_ss(__m128 __a, __m128d __b)`	`CVTSD2SS xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

What the narrowing does#

In compiled code#