CVTSI2SD

CVTSI2SD converts a signed integer of 32 or 64 bits, from a general-purpose register or memory, to a double in the low element of an XMM register. Every 32-bit integer has an exact double; a 64-bit one may need more than the 53 bits of a double’s significand, and is then rounded as MXCSR.RC says and sets the precision flag. GCC 14 and Clang 23 at -O2 compile C’s conversions from int and long to double to it.

The false dependency#

The legacy form writes bits 63:0 and keeps bits 127:64 of the destination, so the old value of that register is an input: the conversion waits for the instruction that last wrote it, although the program wants only the integer converted. AMD’s optimization guide for Zen 5 lists CVTSI2SD among the instructions whose result is merged into the upper part of the destination, and says that the processor skips that wait when it knows those bits to be zero, as after a zeroing idiom such as XORPS of a register with itself (Sections 2.11.5 and 2.11.2). Intel’s guide likewise recommends a dependency-breaking zero idiom where reusing a register creates such a chain (Section 3.5.1.7). The compilers differ in where they put one:

• GCC 14 zeroes the destination before every conversion: pxor xmm0, xmm0, then cvtsi2sd xmm0, edi.
• Clang 23 adds an XORPS before conversions inside loops, but not in a function that converts its argument once.

The VEX form, VCVTSI2SD, takes bits 127:64 from a separate source register and clears the bits above 127. In a loop, GCC zeroes one register before it and names that register as the source in every iteration; Clang names XMM15, which its code never writes.

Unsigned integers#

No form converts an unsigned integer before AVX-512. For a 32-bit unsigned value both compilers zero-extend it to 64 bits and use the 64-bit form, which is exact. For a 64-bit one, GCC converts half the value, keeping its lowest bit so that the rounding comes out right, and doubles the result; Clang avoids CVTSI2SD with a sequence of packed operations. With AVX-512 both use VCVTUSI2SD. CVTSI2SS converts to a single, where 32-bit integers above 2^24 may be rounded too, and CVTDQ2PD converts two packed 32-bit integers, the form vectorized loops use.

In the optimization guide

What the optimization guide says about CVTSI2SD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: Zen 3 to Zen 5 let sqrtss, cvtsi2sd and other scalar instructions skip the wait for an XMM register whose upper part is known to be zero, so AMD advises zeroing a vector register when done with it.
• Partial register and flag writes: LLVM breaks the false dependency itself, with an xorps before cvtsi2sd, sqrtss and the other partial writers whose register was written within the last 64 instructions.

Bulldozer to Excavator

• Vectors and floating point: Scalar instructions such as SQRTSS and CVTSI2SD keep the rest of their destination and wait for its last write, unless the core knows that part to be zero, which it tracks from the instructions that cleared it.

Jaguar and Puma

• Vectors and floating point: Scalar instructions such as SQRTSS and CVTSI2SD keep the rest of their destination and so wait for its last write, unless the core knows that part to be zero: it follows registers whose upper bits an instruction cleared until something nonzero lands there.

Zen and Zen+

• Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination, and so wait for its last write, unless the core knows that part to be zero.

Zen 2

• Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Zen 3

• Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Zen 4

• Vectors and floating point: Scalar instructions such as SQRTSS or cvtsi2sd keep the upper part of their destination and so wait for its last write, except when the core knows that part is zero.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = to_f64(signed(src2))
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSI2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE2 instructions

• ADDPD
• ADDSD
• ANDNPD
• ANDPD
• CMPPD
• CMPSD
• COMISD
• CVTDQ2PD
• CVTDQ2PS
• CVTPD2DQ
• CVTPD2PI
• CVTPD2PS
• CVTPI2PD
• CVTPS2DQ
• CVTPS2PD
• CVTSD2SI
• CVTSD2SS
• CVTSS2SD
• CVTTPD2DQ
• CVTTPD2PI
• CVTTPS2DQ
• CVTTSD2SI
• DIVPD
• DIVSD
• LFENCE
• MASKMOVDQU
• MAXPD
• MAXSD
• MFENCE
• MINPD
• MINSD
• MOVAPD
• MOVD
• MOVDQ2Q
• MOVDQA
• MOVDQU
• MOVHPD
• MOVLPD
• MOVMSKPD
• MOVNTDQ

All 124 SSE2 instructions