CVTSI2SS

CVTSI2SS converts a signed 32-bit or 64-bit integer, from a general-purpose register or memory, to a single in the low element of an XMM register, and keeps bits 127:32. It is what C’s (float) of an int or a long compiles to. CVTSI2SD, its double counterpart, describes the false dependency that comes from keeping the upper bits, how GCC 14 and Clang 23 break it with a zeroing XORPS or PXOR, and the VEX form’s separate source register; all of that applies here unchanged, and AMD’s Zen 5 guide names both conversions among the instructions that can skip the wait (Section 2.11.5).

Rounding#

A single has 24 significant bits, so even 32-bit integers may not fit: beyond 2^24 = 16,777,216, an integer may need rounding, which follows MXCSR.RC and sets PE, the precision flag. The cases recorded on Zen 5 show it:

• 16,777,217 from R9 became 16,777,216 and set PE;
• the 32-bit form converted R14D = 80000000h, the most negative int, exactly to -2^31, ignoring the upper half of R14;
• a 64-bit integer from memory near 2^62 was rounded toward zero, as MXCSR.RC said, and set PE.

Converting a long straight to a single rounds once. Going through a double first rounds twice and can land one unit off, so the 64-bit form is the one to use, and the compilers do.

Unsigned and wide sources#

As for doubles, there is no unsigned form before AVX-512. For a uint32_t, GCC 14 and Clang 23 at -O2 zero-extend it to 64 bits and use the 64-bit form. For a uint64_t with its top bit set, both halve the value, OR the lost lowest bit back in so the rounding comes out right, convert, and double the result with ADDSS. VCVTUSI2SS does it in one instruction.

No packed conversion from 64-bit integers to singles exists before AVX512DQ’s VCVTQQ2PS, so a loop converting an array of long runs one CVTSI2SS per element: GCC as a plain scalar loop, Clang unrolled, joining four results with UNPCKLPS and MOVLHPS before each 16-byte store. An array of int instead becomes CVTDQ2PS, four at a time. The instruction table of AMD’s Zen 5 guide lists the register forms as two macro-ops and the memory forms as one.

In the optimization guide

What the optimization guide says about CVTSI2SS, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Out of order

• Partial register and flag writes: Zen 3 to Zen 5 let sqrtss, cvtsi2sd and other scalar instructions skip the wait for an XMM register whose upper part is known to be zero, so AMD advises zeroing a vector register when done with it.
• Partial register and flag writes: LLVM breaks the false dependency itself, with an xorps before cvtsi2sd, sqrtss and the other partial writers whose register was written within the last 64 instructions.

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f32[0] = to_f32(signed(src2))
# xmm1.d[1] to [3] keep their values
# bits 128 and up of the register are unchanged

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms

follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSI2SS, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More SSE instructions

• ADDPS
• ADDSS
• ANDNPS
• ANDPS
• CMPPS
• CMPSS
• COMISS
• CVTPI2PS
• CVTPS2PI
• CVTSS2SI
• CVTTPS2PI
• CVTTSS2SI
• DIVPS
• DIVSS
• LDMXCSR
• MASKMOVQ
• MAXPS
• MAXSS
• MINPS
• MINSS
• MOVAPS
• MOVHLPS
• MOVHPS
• MOVLHPS
• MOVLPS
• MOVMSKPS
• MOVNTPS
• MOVNTQ
• MOVSS
• MOVUPS
• MULPS
• MULSS
• ORPS
• PAVGB
• PAVGW
• PEXTRW
• PINSRW
• PMAXSW
• PMAXUB
• PMINSW

All 65 SSE instructions