CVTSS2SD instruction (SSE2)

CVTSS2SD converts the low single of a register or of four bytes of memory to a double in the low half of an XMM register. Every single has an exact double, so nothing is rounded and MXCSR.RC plays no part; the only exceptions are invalid for a signaling NaN, which becomes the matching quiet NaN, and denormal for a denormal input. Such an input comes out as an ordinary normal double, since a double’s exponent reaches far below a single’s, unless MXCSR.DAZ is set, which turns it into a zero of the same sign first.

C promotes floats to double in many places that do not look like conversions, and each one is a CVTSS2SD in GCC 14 and Clang 23 at -O2: returning a float from a function declared to return double, mixing a float with a double in an expression, and passing a float to a variadic function such as printf, which receives it as a double. A float multiplied by a double constant needs no conversion when the constant fits a single exactly: both compilers turn x * 0.5 into one MULSS.

The upper half

The legacy form writes bits 63:0 and keeps bits 127:64 of the destination, so it reads the register’s old value and waits for whatever wrote it last, as CVTSI2SD does. The compilers handle this differently for a float in memory: GCC zeroes the destination with PXOR and then converts from memory, while Clang loads the float with MOVSS, which clears the rest of the register, and converts register to register. AMD’s Zen 5 guide lists CVTSS2SD among the instructions that skip the merge when the processor knows the upper bits to be zero (Section 2.11.5).

VCVTSS2SD takes bits 127:64 from a second source and clears the bits above 127, and its EVEX form adds a mask and {sae}. CVTSD2SS goes the other way, rounding as MXCSR says, and CVTPS2PD converts two singles at once.

Forms

Every encoding of CVTSS2SD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTSS2SD xmm, m32` CVTSS2SD_XMMsd_MEMss	`F3 0F 5A /r`	SSE2
`CVTSS2SD xmm, xmm` CVTSS2SD_XMMsd_XMMss	`F3 0F 5A /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Scalar: only the low double is computed; the other double comes from xmm1.

Result double 0 is computed from single 0 of xmm2; double 1 is that of xmm1. Result doubles 1 to 0: a1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.f64[0] = to_f64(src2.f32[0])
# xmm1.q[1] keeps its value
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTSS2SD xmm, xmm/m32`
`xmm`	explicit	read, write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSS2SD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvtss_sd` `__m128d _mm_cvtss_sd(__m128d __a, __m128 __b)`	`CVTSS2SD xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

The upper half#