CVTSS2SI instruction (SSE)

CVTSS2SI converts the low single of an XMM register or of four bytes of memory to a signed integer in a 32-bit or 64-bit general-purpose register, rounding as MXCSR.RC says. Under the default, round to nearest, a value halfway between two integers goes to the even one: 2.5 becomes 2, 3.5 becomes 4 and -0.5 becomes 0. Its sibling CVTTSS2SI always truncates, which is what a C cast asks for; that page also covers what both do with values out of range.

Rounding as the mode says

C’s functions for rounding in the current mode are the ones that map here. With -fno-math-errno, GCC 14 and Clang 23 at -O2 compile lrintf(x) to cvtss2si rax, xmm0, even when the result is then narrowed to an int, since lrintf returns a long; without that option both call the library, as lrintf may set errno. lroundf, which rounds halfway cases away from zero, matches no MXCSR mode and stays a call.

To round another way for one conversion, legacy code changes MXCSR with LDMXCSR around it, which affects every later instruction too. The EVEX form VCVTSS2SI can carry its own rounding mode in the instruction instead, with exceptions suppressed; VCVTSS2USI converts to an unsigned integer.

Recorded on Zen 5

With round toward zero in MXCSR, 1.0000001 converted to 1 and set PE, the inexact flag.
A single too large for 32 bits, 5EFFFFFFh (about 9.2 * 10^18), converted to 80000000h in a 32-bit register and negative infinity to 8000000000000000h in a 64-bit one, the integer indefinite of each size, and both set IE. A 32-bit destination cleared bits 63:32 of the register, as any 32-bit write does.

CVTSD2SI is the version for doubles. AMD’s Zen 5 guide lists CVTSS2SI as two macro-ops, and gives its EVEX form a latency of four cycles.

Forms

Every encoding of CVTSS2SI that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTSS2SI r32, m32` CVTSS2SI_GPR32d_MEMss	`F3 0F 2D /r`	SSE
`CVTSS2SI r32, xmm` CVTSS2SI_GPR32d_XMMss	`F3 0F 2D /r`	SSE
`CVTSS2SI r64, m32` CVTSS2SI_GPR64q_MEMss	`F3 REX.W 0F 2D /r`	SSE
`CVTSS2SI r64, xmm` CVTSS2SI_GPR64q_XMMss	`F3 REX.W 0F 2D /r`	SSE

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

The low single of xmm2 is converted, and the integer goes to r32.

r32 receives the conversion of single 0 of xmm2: r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

a = src2.f32[0]
dest.write(cvt_int(a, dest.bits))  # r32: bits 63:32 cleared

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTSS2SI r32, xmm/m32` `CVTSS2SI r64, xmm/m32`
`r32/64`	explicit	write
`xmm/m32`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_3

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTSS2SI, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvt_ss2si` `int _mm_cvt_ss2si(__m128 __a)`	`CVTSS2SI r32, xmm` Legacy -msse
`_mm_cvtss_si32` `int _mm_cvtss_si32(__m128 __a)`	`CVTSS2SI r32, xmm` Legacy -msse
`_mm_cvtss_si64` `long long _mm_cvtss_si64(__m128 __a)`	`CVTSS2SI r64, xmm` Legacy -msse

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE` SSE	SSE `CPUID.01H:EDX[25]` SSE	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE instructions

All 65 SSE instructions

Rounding as the mode says#

Recorded on Zen 5#