CVTTPD2DQ instruction (SSE2)

CVTTPD2DQ converts the two doubles of an XMM register or of 16 bytes of memory to signed doublewords, truncating toward zero whatever MXCSR.RC says, and writes them to the low 64 bits of the destination, zeroing bits 127:64. Halving the element size halves the result: CVTTPS2DQ turns four singles into four doublewords in place, while this instruction fills only half a register. CVTTSD2SI is the scalar version, and CVTPD2DQ rounds as MXCSR says.

Out-of-range values behave as in the other truncating conversions: a NaN, an infinity or a double that truncates outside -2^31 to 2^31 - 1 gives 80000000H, the integer indefinite, and sets IE. On Zen 5, infinities of both signs and a signaling NaN each gave 80000000H; with IE unmasked, a NaN raised #XM and left the destination alone. Negative zero converted to 0.

Two halves make a vector

GCC 14 and Clang 23 at -O2 compile a loop of out[i] = (int)in[i] over doubles to two CVTTPD2DQs and a shuffle that joins their low halves: PUNPCKLQDQ in GCC, UNPCKLPD in Clang. Both load the doubles with MOVUPD first, since the legacy memory form needs its operand aligned to 16 bytes and the arrays may not be. With -mavx2, VEX’s 256-bit form converts four doubles of a YMM register to an XMM register, and GCC joins two of those with VINSERTI128; with -march=x86-64-v4, GCC uses the 512-bit form, eight doubles to a YMM register.

Mnemonics

The VEX and EVEX forms, on the VCVTTPD2DQ page, read 128, 256 or 512 bits and write half as many, so in AT&T syntax a memory operand does not show which width is meant. GNU as therefore spells the memory forms vcvttpd2dqx and vcvttpd2dqy, as both compilers’ output does; Intel syntax says it with xmmword ptr or ymmword ptr.

AMD’s Zen 5 guide lists CVTTPD2DQ as one macro-op with a latency of three cycles, and the 256-bit VEX form as two with a latency of six.

Forms

Every encoding of CVTTPD2DQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTTPD2DQ xmm, m128` CVTTPD2DQ_XMMdq_MEMpd	`66 0F E6 /r`	SSE2
`CVTTPD2DQ xmm, xmm` CVTTPD2DQ_XMMdq_XMMpd	`66 0F E6 /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Narrow: each double becomes a doubleword, in the same order, at the low end of the result; the rest of the register is zeroed.

Result doublewords 3 to 0: 0, 0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(2):
    xmm1.d[i] = cvtt_int(src2.f64[i], 32)
for i in range(2, 4):
    xmm1.d[i] = 0
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 9 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTTPD2DQ xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTTPD2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvttpd_epi32` `__m128i _mm_cvttpd_epi32(__m128d __a)`	`CVTTPD2DQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Two halves make a vector#

Mnemonics#