CVTTPS2DQ instruction (SSE2)

CVTTPS2DQ converts four singles to signed doublewords, rounding toward zero whatever MXCSR.RC says: -1.5 becomes -1 and 2.9 becomes 2. That is C’s conversion from float to int, so it is what vectorized casts compile to; CVTPS2DQ, without the second T, rounds as MXCSR says instead, and CVTTSS2SI is the scalar version, which also describes the conversion’s limits in detail.

A NaN, an infinity or a value whose integer part lies outside -2^31 to 2^31 - 1 gives 80000000h, the integer indefinite, and sets IE, or raises #XM if IE is unmasked. The cases recorded on Zen 5, with IE masked, show it for 2^32 and for a value just below -2^31, beside 2,147,483,520, the largest single under 2^31, converting exactly to 7FFFFF80h.

Vectorized casts

GCC 14 and Clang 23 at -O2 compile a loop of out[i] = (int)in[i] over 1,024 elements to CVTTPS2DQ with the input as its memory operand. With the count a function argument, only Clang vectorizes it; GCC converts one element at a time with CVTTSS2SI.

For (unsigned)in[i] there is no SSE conversion, and the compilers build one from CVTTPS2DQ in different ways:

GCC compares each element with 2^31, subtracts 2^31 from those not below it, converts, and sets bit 31 of the same elements with an XOR.
Clang converts both x and x - 2^31. Where x is 2^31 or more, the first result is the indefinite 80000000h; an arithmetic shift by 31 turns its sign into a mask that selects the second result, ORed with that 80000000h. The out-of-range answer is put to use.

With AVX-512F both compilers use VCVTTPS2UDQ instead.

Other forms

VCVTTPS2DQ is the VEX and EVEX form, with masking, broadcast and {sae} in the latter, and VCVTTPS2DQS (AVX10.2) saturates out-of-range values instead of giving the indefinite. CVTTPD2DQ converts two doubles. The legacy form with a memory operand needs it aligned to 16 bytes. The instruction table of AMD’s Zen 5 guide lists CVTTPS2DQ as one macro-op with a latency of three cycles.

Forms

Every encoding of CVTTPS2DQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`CVTTPS2DQ xmm, m128` CVTTPS2DQ_XMMdq_MEMps	`F3 0F 5B /r`	SSE2
`CVTTPS2DQ xmm, xmm` CVTTPS2DQ_XMMdq_XMMps	`F3 0F 5B /r`	SSE2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each single of the result comes from the single in the same place in each source.

Result single i comes from single i of xmm2. Result singles 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(4):
    xmm1.d[i] = cvtt_int(src2.f32[i], 32)
# bits 128 and up of the register are unchanged

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`CVTTPS2DQ xmm, xmm/m128`
`xmm`	explicit	write
`xmm/m128`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: SSE_TYPE_2

Attributes

What else XED records about the forms. How to read.

All forms: follows MXCSR
Memory forms: aligned memory operand

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to CVTTPS2DQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_cvttps_epi32` `__m128i _mm_cvttps_epi32(__m128 __a)`	`CVTTPS2DQ xmm, xmm` Legacy -msse2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`SSE2` SSE2	SSE2 `CPUID.01H:EDX[26]` SSE2	Every x86-64 processor in XED’s model and Zen 3 to Zen 6

More SSE2 instructions

All 124 SSE2 instructions

Vectorized casts#

Other forms#